Air Gap Memory Device Reduces Word Line Capacitance
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Solution Overview
Problem
As memory devices become smaller and more integrated, the capacitance effect between the word line and the bit line becomes significant, causing program disturbance that affects the performance of memory cells or arrays, necessitating a reduction of this capacitance effect.
Innovation Solution
The formation of air gaps with wide and narrow portions alternately arranged between the stack structures and conductive layers, utilizing the insulating properties of air to reduce capacitance, is achieved through a method involving the alternation of conductive and dielectric layers and selective etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are made smaller with higher integration, then storage capability is improved, but capacitance effect between word line and bit line increases causing program disturbance
Solution Approach 1:
An air gap is introduced as an intermediary insulating layer between the word line (third conductive layer) and the bit line (first conductive layer). This air gap acts as a mediator to reduce the capacitance coupling between these two conductive layers, thereby preventing program disturbance while maintaining the high-density memory structure.
Solution Approach 2:
The dielectric constant of the medium between conductive layers is changed by replacing solid dielectric material with air (which has a lower dielectric constant). This parameter change reduces the capacitance effect between the word line and bit line, addressing the program disturbance issue in high-density memory devices.
2Object-affected harmful factors
If air gaps are formed between stack structures and conductive layers, then capacitance effect is reduced, but device complexity increases
Solution Approach 1:
The continuous dielectric layer between the stack structures and conductive layers is segmented into discrete air gaps. These air gaps are formed at specific locations where capacitance reduction is most needed, allowing the structure to maintain simplicity in non-critical areas while reducing capacitance in critical overlapping regions.
Solution Approach 2:
Air gaps are not uniformly distributed but are strategically placed in local regions where the word line and bit line overlap. This local application of the air gap structure reduces capacitance effect precisely where it causes program disturbance, while avoiding unnecessary complexity in areas where capacitance is not problematic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes the capacitance effect between conductive layers, preventing program disturbance and enhancing the performance of memory cells or arrays by leveraging the low dielectric constant of air as an insulating medium.
Implementation Method 1
utilizing the insulating properties of air to reduce capacitance... leveraging the low dielectric constant of air as an insulating medium
Data Source
AI summary
The memory device is provided to include a substrate, a plurality of stack structures, conductive pillars, charge storage layers, and third conductive layers. The stack structures are arranged along a first direction and extend along a second direction, wherein each stack structure includes a plurality of first conductive layers and a plurality of dielectric layers that are alternately stacked along a third direction. Each conductive pillar is located on the substrate between two adjacent stack structures. Each charge storage layer is disposed between the stack structures and the conductive pillars. Each third conductive layer extending along the first direction overlaps the stack structures in a plurality of overlapped regions and covers a portion of top parts of the stack structures and the conductive pillars. An air gap is formed along the third direction in each overlapped region where the stacked structures and the third conductive layers overlap.