Air-Gap Interconnect Layout for Dense Semiconductor Routing
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Solution Overview
Problem
As semiconductor fabrication progresses to smaller technology nodes, increased capacitances in interconnect structures between adjacent metal lines degrade device performance, leading to reduced device speed, and existing interconnect technologies are not satisfactory in addressing this issue without excessive cost increases.
Innovation Solution
The formation of air gaps between adjacent metal lines within a dielectric layer, combined with the use of protecting layers and advanced etching processes like advanced chemical oxide removal (aCOR), reduces capacitances and improves device performance by forming improved interconnect structures with reduced capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch between adjacent metal lines is reduced to increase functional density, then the number of interconnected devices per chip area increases, but the capacitance between adjacent metal lines increases leading to degraded device speeds
Solution Approach 1:
An air gap is introduced as an intermediary layer between adjacent metal lines. This air gap acts as a mediator that reduces the capacitance coupling between the metal lines while maintaining their electrical connectivity through conductive plugs. The air gap has lower dielectric constant than traditional dielectric materials, thereby reducing parasitic capacitance and improving signal speed despite reduced pitch.
Solution Approach 2:
The patent utilizes an air gap (a porous structure with air as the filling material) between adjacent metal lines. The air-filled porous structure reduces the effective dielectric constant in the interconnect region, thereby reducing capacitance between adjacent conductors and improving device speed while maintaining high functional density.
2Speed
If air gaps are formed between adjacent metal lines to reduce capacitance, then device speed improves, but the fabrication process complexity increases due to additional processing steps
Solution Approach 1:
The air gap formation is integrated into the existing interconnect fabrication sequence by performing selective removal of dielectric material after metal line deposition but before final planarization. This preliminary action creates the air gaps at the optimal stage in the process flow, allowing subsequent conformal deposition and planarization steps to complete the structure without requiring entirely new process modules.
Solution Approach 2:
The fabrication process utilizes self-aligned deposition and planarization techniques where the air gap structure itself guides the subsequent processing steps. The conformal dielectric deposition automatically conforms to the air gap geometry, and chemical mechanical polishing (CMP) automatically planarizes the surface, reducing the need for additional alignment and correction steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitances by 10% to 20%, enhancing device speed and performance while maintaining cost efficiency, as demonstrated in the semiconductor device fabrication process.
Implementation Method 1
capacitances between adjacent metal lines increase as the pitch shrinks. Such capacitance increase has been shown to lead to degraded device speeds
Data Source
AI summary
In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.