Air-Gap Ruthenium MOL Interconnect for Lower RC Delay

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Solution Overview

Problem

The integration circuit (IC) industry faces challenges in reducing resistance-capacitance (RC) delay due to high contact resistances and capacitances in middle-of-line (MOL) interconnect structures, which hinder signal routing efficiency and limit further scaling down of ICs.

Innovation Solution

A novel MOL interconnect structure is proposed, featuring a ruthenium layer with an air gap between the ruthenium structure and the insulator layer, reducing capacitance and resistance, and a method for fabricating this structure involving multiple layers and etching processes to form a device-level contact, adhesion layer, and patterned mask features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional MOL interconnect structures are used, then manufacturing process is simpler, but RC delay increases due to high contact resistance and capacitance

Engineering Contradiction:
ImproveRC delayVSAvoidinterconnect structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interconnect structure is segmented into distinct functional layers: a first insulator layer for electrical isolation, a ruthenium layer for low-resistance conduction, and a second insulator layer for capacitance reduction. This segmentation allows each layer to optimize its specific function, reducing overall RC delay while maintaining manufacturability through standardized layer-by-layer fabrication processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs composite material architecture by combining ruthenium (a low-resistance metal) with dual insulator layers (providing electrical isolation and capacitance management). This composite structure leverages the complementary properties of each material: ruthenium minimizes resistance, while the insulator layers minimize capacitance and provide electrical isolation, collectively reducing RC delay without significantly complicating the manufacturing process.

Inventive Principle:
Principle #40Composite materials

2Quantity of substance

If geometry size is reduced to increase functional density, then more IC devices fit per chip area, but RC delay increases due to material limitations

Engineering Contradiction:
Improvefunctional densityVSAvoidRC delay
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent changes the material parameters of the interconnect structure by introducing ruthenium with superior electrical conductivity and implementing a dual-layer insulator configuration. These parameter changes (material composition and structural configuration) enable the maintenance of low RC delay even as geometry dimensions are reduced to increase functional density, effectively decoupling scaling from RC delay degradation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively decreases RC delay, improves IC device performance by reducing parasitic capacitance and resistance, and facilitates better electrical current flow, thereby enhancing the performance of advanced IC technology nodes.

Implementation Method 1

capacitance (C) (i.e., a material's ability to store electrical charge). Reducing both resistance and capacitance is thus desired to reduce RC delay

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

resistance (R) (i.e., a material's opposition to flow of electrical current)

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS12142520B2Middle-of-line interconnect structure having air gap and method of fabrication thereof
Publication Date: 2024.11.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12142520B2 patent drawing
  • US12142520B2 patent drawing
  • US12142520B2 patent drawing

AI summary

Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.