Air Gap MOS Transistor for RF Circuit Parasitic Charge Isolation
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Solution Overview
Problem
In RF integrated circuit applications, such as RF switch devices and power amplifiers, the 'parasitic surface charge' issue leads to harmonic effects, and current solutions like using semiconductor-on-insulator (SOI) wafers are costly, necessitating a method to improve performance while reducing costs.
Innovation Solution
A method involving a substrate with silicon layers and an insulating layer, where a metal-oxide semiconductor (MOS) transistor is formed, and a wet etching process is used to create air gaps under the transistor, reducing capacitance by forming a U-shaped air gap in the insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI wafer or substrate is used to isolate charges, then performance is improved, but cost increases
Solution Approach 1:
The patent extracts the essential function of charge isolation from the expensive SOI wafer structure and implements it through a localized air gap formed by removing insulating layer material. This separates the charge isolation function from the entire SOI substrate requirement, achieving the same electrical isolation effect with a simpler, cheaper structure.
Solution Approach 2:
The patent replaces the expensive SOI wafer with a conventional wafer plus a selectively removed insulating layer. The air gap structure achieves charge isolation using inexpensive process steps (etching existing insulating layer) rather than requiring costly specialized substrates.
2Object-generated harmful factors
If air gap is formed under MOS transistor, then capacitance is reduced, but process complexity increases
Solution Approach 1:
The patent forms the air gap structure during the interlayer dielectric formation process, before final device assembly. The insulating layer is removed in a trench pattern to create the air gap, and then the trench is filled with dielectric material. This preliminary formation integrates the air gap creation into the existing process flow without requiring separate complex steps.
Solution Approach 2:
The patent uses the interlayer dielectric layer to serve multiple functions: it provides mechanical support, electrical isolation, and forms the structure that will become the air gap after selective removal. The same dielectric material fills both the air gap region and the planarization layer, reducing the number of different materials required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance and improves performance without the high cost associated with SOI wafers, enhancing the efficiency of RF integrated circuits.
Implementation Method 1
performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.