Air Gap Formation in Semiconductor Interconnects

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Solution Overview

Problem

As semiconductor devices are miniaturized, they experience RC delay due to parasitic resistance and capacitance, which existing methods such as copper wiring and ultra-low k materials fail to adequately address, leading to delayed signal transmission.

Innovation Solution

A semiconductor device and manufacturing method that incorporates a phase change material layer between metal wires, with a thermal process inducing a phase change to create an air gap, reducing parasitic capacitance and thereby minimizing RC delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If oxide and metal materials are used in semiconductor devices, then electrical signal transmission is enabled, but parasitic resistance and parasitic capacitance are generated causing RC delay

Engineering Contradiction:
Improvesignal transmission speedVSAvoidparasitic resistance and parasitic capacitance
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the harmful dielectric material (IMD) from the region between adjacent metal wires and replaces it with an air gap. This removal eliminates the source of parasitic capacitance that causes RC delay, while preserving the electrical connection function of the metal wires. The air gap acts as a void space that provides electrical isolation without introducing parasitic capacitance.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the dielectric constant parameter by replacing the IMD material (with high dielectric constant) with air (with dielectric constant approximately equal to 1). This parameter change directly reduces parasitic capacitance between adjacent metal wires, thereby reducing RC delay and improving signal transmission speed.

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If copper wiring and ultra low-k materials are used to reduce parasitic resistance, then signal transmission is improved, but materials still exhibit parasitic resistance and parasitic capacitance

Engineering Contradiction:
Improveparasitic resistance and parasitic capacitanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent uses a sacrificial material (such as organic material or polymer) that is deposited between metal wires and then completely removed through thermal treatment. This sacrificial material serves only as a temporary placeholder during manufacturing, enabling the formation of air gaps without requiring complex direct etching or deposition processes. The simplicity of using and removing sacrificial material reduces overall manufacturing complexity.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent utilizes phase transition of the sacrificial material from solid to gas/vapor through thermal decomposition or combustion. This phase transition enables complete removal of the sacrificial material, creating air gaps between metal wires. The phase change process is simple and effective, avoiding complex material removal techniques while achieving the desired air gap structure.

Inventive Principle:
Principle #36Phase transitions

3Speed

If air gap is formed between metal wires to reduce parasitic capacitance, then RC delay is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improvesignal transmission speedVSAvoidmanufacturing process complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent performs preliminary deposition of sacrificial material between metal wires before final device completion. This preliminary action simplifies the overall process because the sacrificial material is already in place, and subsequent thermal treatment automatically creates the air gaps. This approach avoids complex post-processing steps and integrates air gap formation into the existing manufacturing flow.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial material performs multiple functions automatically: it defines the air gap geometry during deposition, maintains structural integrity during subsequent processing steps, and self-removes through thermal treatment to create the final air gap structure. This self-service capability reduces the need for additional specialized process steps, thereby reducing manufacturing complexity despite the advanced functionality achieved.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method significantly reduces RC delay by forming an air gap between metal wires, decreasing capacitance and enhancing signal transmission speed.

Implementation Method 1

performing a thermal process for inducing a change of a phase of the phase change material layer

Methodology Applied
Scientific EffectPhase change: Phase Change

Implementation Method 2

By performing a thermal process for inducing a change of a phase of the phase change material after a phase change material is formed between the metal wires, a semiconductor device in which a predetermined air layer is formed between the metal wires

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS8071971B2Semiconductor device including air gap
Publication Date: 2011.12.06 MARVELL ASIA PTE LTD
  • US8071971B2 patent drawing
  • US8071971B2 patent drawing
  • US8071971B2 patent drawing

AI summary

Embodiments relate to a semiconductor device, and more particularly, to a semiconductor device and a manufacturing method thereof that can reduce RC delay within the semiconductor device. Embodiments provide a semiconductor device including: a first interlayer dielectric layer formed over the a semiconductor substrate, a first metal wire and a second metal wire formed over the first interlayer dielectric layer, a second interlayer dielectric layer formed over the first and second metal wires, and a phase change material layer formed between the first and second metal wires.