Air-Replaced Spacer Structure for Self-Aligned Contact RC Delay
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the RC delay of CMOS transistors due to high dielectric capacitance between gate and source/drain structures, which hinders performance improvements in semiconductor devices.
Innovation Solution
The implementation of air-replaced spacers with a low dielectric constant of about 1, formed between the gate structure and self-aligned source/drain contact structures, reduces capacitance by using a dummy silicon spacer and tuning its size, along with a silicon nitride layer to prevent silicide extrusion and damage to epitaxial structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric spacers are used between gate and source/drain structures, then structural support and isolation are provided, but high dielectric capacitance increases RC delay and degrades device performance
Solution Approach 1:
The patent changes the dielectric constant parameter of the spacer material from conventional high-k dielectric materials to air (k≈1) by removing the spacer material entirely, thereby reducing capacitance and RC delay while maintaining the structural isolation function through alternative means
Solution Approach 2:
The patent extracts the spacer material from the structure completely, replacing it with air, thereby eliminating the dielectric capacitance contribution from the spacer while maintaining the necessary structural support through the self-aligned contact scheme and surrounding dielectric structures
2Loss of energy
If spacer material is removed to reduce capacitance, then dielectric constant is reduced, but structural support and alignment functions must be maintained
Solution Approach 1:
The patent employs a self-aligned contact scheme where the contact structures automatically align with the gate structure through the etching process itself, eliminating the need for separate alignment steps and maintaining manufacturing precision without requiring physical spacer materials
Solution Approach 2:
The patent uses air as an intermediary between the gate and contact structures, providing electrical isolation and reduced capacitance while allowing the self-aligned etching process to maintain precise spatial relationships without requiring solid spacer materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device AC performance by at least 1.5% compared to CMOS transistors without air-replaced spacers, while maintaining comparable DC performance, by reducing the dielectric constant and capacitance between the gate and source/drain structures.
Implementation Method 1
air-replaced spacers with a low dielectric constant of about 1, formed between the gate structure and self-aligned source/drain contact structures, reduces capacitance
Data Source
AI summary
The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.