Air-Gap Semiconductor Device With Dual Barrier Step Coverage
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Solution Overview
Problem
As semiconductor devices become more fine and integrated, the narrowing of metal interconnection pitches leads to increased parasitic capacitance, which reduces operating speeds. Existing research has focused on low-resistance metal interconnections and low-dielectric constant dielectrics to mitigate this issue but has not effectively addressed the problem.
Innovation Solution
A semiconductor device design that includes a substrate with a recess region covered by a barrier layer comprising a first and second barrier layer with different step coverages, and an interlayer dielectric layer that defines an air gap within the recess region, allowing for the adjustment of deposition thicknesses to meet diverse thickness conditions and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal interconnection pitches are narrowed to achieve fine and high integration, then device integration is improved, but parasitic capacitance increases and operating speed decreases
Solution Approach 1:
The patent extracts the problematic dielectric material from the recess region and replaces it with an air gap. By removing the solid dielectric material that causes parasitic capacitance and replacing it with air (vacuum), the parasitic capacitance is significantly reduced, thereby improving operating speed while maintaining fine integration
Solution Approach 2:
The patent introduces a porous structure (air gap) into the recess region instead of using solid dielectric material. The air gap acts as a porous/void structure with extremely low dielectric constant, effectively reducing parasitic capacitance between adjacent metal interconnections while preserving the fine-pitch integration
2Device complexity
If a single barrier layer is used to cover the recess region, then the structure is simple, but it is difficult to meet diverse thickness conditions on the inner sidewall and top surface
Solution Approach 1:
The patent segments the barrier layer into multiple distinct layers (first barrier layer and second barrier layer) with different step coverage characteristics. The first barrier layer provides good step coverage for conformal deposition, while the second barrier layer allows for thickness variation, enabling precise control of barrier thickness on both the inner sidewall and top surface of the recess region
Solution Approach 2:
The patent applies different barrier layer materials or deposition conditions to different regions of the recess structure. By using multiple barrier layers with different step coverage properties, each layer can be optimized for specific regions (sidewall vs. top surface), achieving the required thickness precision locally across different surfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces parasitic capacitance by creating an air gap with a low dielectric constant, enhancing the reliability and performance of semiconductor devices by allowing for precise control of barrier layer thicknesses and step coverages, thereby improving operating speeds.
Implementation Method 1
an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region
Data Source
AI summary
A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.