Air Gap Formation in Semiconductor Conductive Structures

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Solution Overview

Problem

In semiconductor device manufacturing, parasitic capacitance between adjacent layers degrades performance and reliability, and existing methods struggle to form air gaps without damaging conductive layers or efficiently removing byproducts.

Innovation Solution

A method involving repeated dry cleaning and purge operations using plasma-less gases like NH3, HF, NF3, and IPA to form and maintain air gaps between conductive structures without damaging adjacent layers, with temperature and pressure control to sublimate byproducts and achieve target width and depth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If a dielectric material having a low dielectric constant is interposed between adjacent layers to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity and manufacturing complexity increase

Engineering Contradiction:
Improveparasitic capacitanceVSAvoiddevice complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent extracts the dielectric material completely from the space between adjacent conductive layers, creating an air gap instead. This removes the harmful parasitic capacitance source while avoiding the complexity of handling and integrating low-k dielectric materials. The air gap is formed by selectively removing the insulation layer in specific regions, thereby eliminating the need to introduce foreign dielectric materials into the device structure.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses air (an inert atmosphere) as the dielectric medium between adjacent conductive layers. By filling the space with air instead of using complex low-k dielectric materials, the patent reduces parasitic capacitance while maintaining manufacturing simplicity. The inert air environment prevents chemical reactions and material degradation that would occur with other dielectric materials.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Object-generated harmful factors

If an air gap is formed between adjacent conductive layers to reduce parasitic capacitance, then parasitic capacitance is reduced, but adjacent conductive layers may be damaged

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidconductive layer integrity
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent segments the insulation layer removal process into multiple stages: first removing the insulation layer in a first region to form an air gap, then selectively removing it in a second region while preserving it in a third region. This segmented approach allows precise control over where air gaps are formed, ensuring they are created only in non-critical areas away from conductive layers, thus reducing parasitic capacitance without damaging the conductive structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses the insulation layer as an intermediary protective barrier during the air gap formation process. By selectively removing the insulation layer in specific regions while maintaining it in others, the patent creates air gaps in safe zones that do not expose conductive layers to damage. The remaining insulation layer acts as a protective mediator that shields vulnerable conductive structures from the effects of air gap formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If dry cleaning operations are performed to form air gaps, then air gaps are formed without damaging conductive layers, but byproducts accumulate and require repeated operations

Engineering Contradiction:
Improveconductive layer integrityVSAvoidmanufacturing cycle time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent employs periodic alternating operations of dry cleaning and purge steps. The dry cleaning operation removes the insulation layer to form air gaps, while the subsequent purge operation removes accumulated byproducts. This periodic alternation allows the system to achieve complete insulation layer removal and byproduct elimination without requiring excessive continuous processing time, thereby forming air gaps reliably without damaging conductive layers while minimizing manufacturing cycle time.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent maintains continuous progress toward air gap formation by seamlessly alternating between dry cleaning and purge operations. Rather than completing one operation fully before starting the next, the method continuously cycles through these steps, ensuring that air gap formation and byproduct removal proceed simultaneously and efficiently. This continuous action eliminates idle time and ensures optimal use of processing resources.

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively reduces parasitic capacitance by forming narrow and deep air gaps without damaging conductive layers, improving semiconductor device performance and reliability.

Implementation Method 1

a first dry cleaning operation to remove a portion of the insulation layer

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Implementation Method 2

performing a first purge operation to remove a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation

Methodology Applied
Scientific EffectSublimation: Sublimation

Data Source

PatentUS10297495B2Method of manufactuing semiconductor device
Publication Date: 2019.05.21 SAMSUNG ELECTRONICS CO LTD
  • US10297495B2 patent drawing
  • US10297495B2 patent drawing
  • US10297495B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.