Air Gap Formation in Semiconductor Contact Over Active Gate Structures
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Solution Overview
Problem
Current semiconductor structures with the contact over active gate (COAG) process suffer from excessive parasitic capacitance between the gate and source/drain plugs, leading to poor performance due to the conventional placement of gate contact plugs in isolation areas.
Innovation Solution
A method is introduced to form a semiconductor structure with a sacrificial side wall layer that occupies space for a first gap, which is then removed to expose the side walls of the gate and source/drain plugs, and sealed with a sealing layer to create an air gap with a lower dielectric constant, reducing parasitic capacitance and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate contact plug is placed in the isolation area above the gate structure, then the manufacturing process is simpler, but the parasitic capacitance between the gate and source/drain plugs increases, degrading device performance
Solution Approach 1:
The patent introduces a vertical air gap dimension between the gate contact plug and source/drain contact plugs by removing the bottom dielectric layer in specific regions. This vertical separation in the Z-dimension effectively reduces parasitic capacitance without changing the horizontal layout, resolving the contradiction between manufacturing simplicity and performance.
Solution Approach 2:
The patent applies local quality by selectively removing the bottom dielectric layer only in regions where air gaps are needed (between gate and source/drain contacts), while preserving the dielectric layer in other areas. This localized modification reduces parasitic capacitance precisely where needed without complicating the overall manufacturing process.
2Productivity
If the critical dimensions are reduced to increase circuit density, then more circuits can be integrated, but the wafer surface area becomes insufficient for required lines
Solution Approach 1:
The patent utilizes the vertical dimension by forming air gaps between layers, enabling three-dimensional interconnect structures. This allows more interconnect lines to be packed into the same wafer surface area by stacking them vertically, thereby increasing circuit density without requiring additional wafer area.
Solution Approach 2:
The patent implements nested interconnect structures where multiple metal layers and contact plugs are vertically stacked and interconnected. The gate contact plug is nested above the gate structure, and source/drain contact plugs are nested above the source/drain regions, with air gaps providing electrical isolation. This nesting approach maximizes the use of vertical space to increase circuit density.
3Area of stationary object
If the contact over active gate (COAG) process is used to place the gate contact plug above the gate structure in the active area, then the chip area is reduced, but the parasitic capacitance between the gate and source/drain plugs increases
Solution Approach 1:
The patent applies local quality by selectively removing the bottom dielectric layer only in the regions between the gate contact plug and source/drain contact plugs, while preserving it elsewhere. This creates localized air gaps that reduce parasitic capacitance precisely where the COAG structure places the contacts in close proximity, without affecting the overall chip area benefits of the COAG process.
Solution Approach 2:
The patent introduces a vertical air gap dimension between the gate and source/drain contact plugs by removing the bottom dielectric layer. This vertical separation in the Z-dimension effectively reduces parasitic capacitance while maintaining the horizontal area savings achieved by the COAG process, as the contact plugs remain positioned above the active area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gap significantly reduces parasitic capacitance and resistance-capacitance delay, enhancing the semiconductor structure's performance by utilizing a lower dielectric constant material compared to conventional dielectric materials.
Implementation Method 1
The air gap has a lower dielectric constant than the dielectric material, which is beneficial to reduce parasitic capacitance between the gate plug and the source/drain plug
Data Source
AI summary
A semiconductor structure and a forming method therefor are provided. The forming method includes: providing a base, a gate structure, a source/drain doped area, and a bottom dielectric layer; forming a source/drain interconnect layer running through the bottom dielectric layer on a top of the source/drain doped area; forming a top dielectric layer on the bottom dielectric layer; forming a gate contact running through the top dielectric layer on a top of the gate structure and a source/drain contact running through the top dielectric layer on a top of the source/drain interconnect layer; forming a sacrificial side wall layer on side walls of the gate contact and the source/drain contact; forming a gate plug filling the gate contact and a source/drain plug filling the source/drain contact; removing the sacrificial side wall layer to form a first gap; and forming a sealing layer sealing the first gap.