Air Gap Formation in Semiconductor Interconnects
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Solution Overview
Problem
As device feature size decreases, interconnects in semiconductor devices face increased electrical resistivity and detrimental capacitance, which existing technologies attempt to mitigate through ultra-low k dielectric materials and air gaps, but effective methods for forming air gaps in advanced metallization schemes are limited.
Innovation Solution
A method involving a gas pulse sequence with precursor gases to form air gaps between raised features in semiconductor devices, where the sequence includes non-conformal and conformal deposition of precursor layers, and optional plasma-excited halogen treatment to control layer formation and achieve air gap creation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If device feature size is scaled down, then device density and integration are improved, but electrical resistivity increases and capacitance between adjacent features increases
Solution Approach 1:
The patent introduces air gaps (porous structures with k≈1) between adjacent interconnect features to reduce capacitance. The air gaps are formed by depositing a sacrificial material and then removing it, creating void spaces that lower the dielectric constant of the surrounding medium and thereby reduce capacitive coupling between neighboring interconnects.
Solution Approach 2:
The patent employs a composite structure combining solid interconnect features with air gap regions. The air gaps act as a dielectric composite material with extremely low k-value (approximately 1), creating a hybrid structure that reduces capacitance while maintaining the mechanical and electrical integrity of the interconnect system.
2Reliability
If air gaps are added to critical layers, then capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary deposition of a sacrificial material layer onto the interconnect structure before final processing. This preliminary action creates a template that defines where air gaps will eventually form, simplifying the overall process by establishing the air gap pattern early in the manufacturing sequence rather than attempting to create voids directly.
Solution Approach 2:
The patent removes the sacrificial material layer after it has served its purpose as a template for air gap formation. This extraction step creates the actual air gaps between interconnect features. The sacrificial material is removed through selective etching or dissolution, leaving behind the desired void spaces without requiring direct manipulation of the final air gap structure.
3Manufacturing precision
If non-conformal deposition is used to form precursor layers, then material coverage is controlled selectively, but process complexity increases
Solution Approach 1:
The patent employs non-conformal deposition techniques where the precursor material is deposited with varying thickness or presence across different regions of the substrate. This local quality variation ensures that material is deposited preferentially in certain areas (such as on top surfaces of interconnects) while avoiding or minimizing deposition in other areas (such as in gaps between features), enabling selective material placement without requiring complex multi-step conformal deposition and patterning sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively forms air gaps, reducing capacitance and improving semiconductor device performance by precisely controlling the deposition of materials between features, enhancing the semiconductor device's electrical properties.
Implementation Method 1
exposing the substrate to a gas pulse sequence to deposit a material that forms an air gap between the raised features
Implementation Method 2
exposing the substrate to a plasma-excited halogen-containing gas to deactivate or at least partially remove the first precursor layer
Data Source
AI summary
A method of fabricating air gaps in advanced semiconductor devices for low capacitance interconnects. The method includes exposing a substrate to a gas pulse sequence to deposit a material that forms an air gap between raised features.