Air-Gap Epitaxial Source/Drain Structure for Nanosheet Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional nanosheet-based transistors suffer from dislocations in source/drain features due to lattice structure differences, leading to degraded crystal quality and reduced device performance.
Innovation Solution
The implementation of epitaxial source/drain features with air gaps between the source/drain features and inner spacers to minimize dislocation formation, achieved through selective epitaxial growth processes that control deposition and etching conditions to prevent merging on sidewall surfaces of inner spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional nanosheet-based transistors are fabricated without air gaps, then the manufacturing process is simpler, but dislocations occur in source/drain features due to lattice structure differences, degrading crystal quality and device performance
Solution Approach 1:
The patent introduces air gaps that segment the interface between source/drain features and inner spacers, separating the crystal growth regions from the spacer regions. This segmentation prevents dislocation propagation by creating a physical barrier, thereby improving device performance without requiring complete structural redesign
Solution Approach 2:
The air gap acts as an intermediary element between the source/drain features and inner spacers. This intermediary prevents direct contact between the lattice structures, eliminating the dislocation mechanism while maintaining the necessary structural relationships for device operation
2Manufacturing precision
If epitaxial source/drain features are grown to fully fill the trench, then the crystal quality is maximized, but the source/drain features merge on the sidewall surfaces of inner spacers, causing dislocations
Solution Approach 1:
The patent applies partial action by growing the epitaxial source/drain features to fill only a portion of the trench space, deliberately leaving air gaps at the sidewall interfaces. This partial filling achieves sufficient crystal quality for device operation while preventing the harmful merging and dislocation formation that would occur with complete filling
3Reliability
If inner spacers are formed with larger dimensions, then the electrical isolation is improved, but the source/drain features must be grown larger, increasing the risk of merging and dislocation formation
Solution Approach 1:
The patent resolves the dimensional conflict by transitioning from a purely lateral dimension approach to a three-dimensional solution. Air gaps are formed that extend vertically along the sidewalls, providing electrical isolation through the vertical dimension while maintaining horizontal spacing that prevents merging. This dimensional approach allows both larger inner spacers for isolation and controlled source/drain growth to avoid dislocations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances crystal quality and device performance by reducing dislocations and maintaining proper electrical isolation, thereby improving the overall efficiency and reliability of nanosheet-based transistors.
Implementation Method 1
growing the source/drain features in the source/drain trenches using the selected growth condition
Data Source
AI summary
A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.