Air Gap Spacer Reduces Parasitic Capacitance in Semiconductor Devices
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Solution Overview
Problem
In semiconductor devices like DRAM, the parasitic capacitance between bit lines and storage node contact plugs increases due to the high dielectric constant of silicon nitride spacers, leading to a decreased sensing margin as devices shrink in size.
Innovation Solution
A semiconductor device with a damascene pattern and conductive patterns separated by a spacer that includes an air gap, where the spacer can be composed of silicon nitride layers, and a sacrificial spacer is used to form the air gap, reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon nitride layer is used as a spacer between bit lines and storage node contact plugs, then the spacer provides structural support and separation, but the high dielectric constant of silicon nitride increases parasitic capacitance
Solution Approach 1:
The patent changes the dielectric parameter of the spacer material from high-k silicon nitride to low-k air gap, fundamentally altering the electrical characteristic while maintaining the mechanical separation function. This parameter change directly reduces parasitic capacitance between bit lines and storage node contact plugs.
Solution Approach 2:
The air gap acts as an intermediary medium between the bit line and storage node contact plug, providing electrical isolation with minimal parasitic capacitance. The sacrificial spacer serves as a temporary intermediary structure that enables the formation of the air gap through selective removal.
2Area of stationary object
If the spacer thickness is reduced to maintain small device area, then the device size decreases, but the parasitic capacitance between bit lines and storage node contact plugs increases
Solution Approach 1:
The patent changes the dielectric parameter of the spacer material from high-k silicon nitride to low-k air gap, fundamentally altering the electrical characteristic while maintaining the mechanical separation function. This parameter change directly reduces parasitic capacitance between bit lines and storage node contact plugs.
3Object-affected harmful factors
If a sacrificial spacer is formed and then removed to create an air gap, then parasitic capacitance is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The sacrificial spacer is formed in advance during the spacer formation process, enabling subsequent selective removal to create the air gap. This preliminary action integrates the air gap formation into the existing manufacturing flow without requiring separate process steps.
Solution Approach 2:
The sacrificial spacer material is selectively removed through etching processes, extracting the temporary structure to leave behind the desired air gap. This extraction method is compatible with standard semiconductor manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gap reduces parasitic capacitance between bit lines and storage node contact plugs, enhancing the sensing margin and enabling the fabrication of smaller semiconductor devices with improved characteristics.
Implementation Method 1
the parasitic capacitance (Cb) between bit lines and storage node contact plugs
Implementation Method 2
The spacer is typically a nitride layer, such as a silicon nitride layer. Generally, a silicon nitride layer has a high dielectric rate
Data Source
AI summary
A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.