Air-Gap Spacer Structure for Integrated Circuit Parasitic Capacitance Reduction
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Solution Overview
Problem
The increasing density of conductive patterns in integrated circuit devices has led to increased parasitic capacitance, which affects the performance and reliability of these devices.
Innovation Solution
The integration of a pair of spacers on a substrate with a recess, a lower conductive pattern, and an upper conductive pattern that exposes a portion of its surface, along with a capping pattern that seals a cavity under it, helps reduce parasitic capacitance by creating an air-gap or void structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If distances between conductive patterns are reduced to increase density, then device density is improved, but parasitic capacitance increases
Solution Approach 1:
An air-gap spacer is introduced as an intermediary substance between the first and second conductive patterns. This spacer creates a physical separation that reduces parasitic capacitance while allowing the conductive patterns to remain in close proximity for high density. The spacer acts as a mediator that enables both high density and low capacitance simultaneously.
Solution Approach 2:
The solution moves from two-dimensional planar spacing to three-dimensional vertical spacing by forming an air-gap spacer that extends from the substrate surface up to contact the conductive patterns. This vertical dimension allows for reduced parasitic capacitance without compromising horizontal density.
2Productivity
If conductive patterns are placed closer together, then integration density is improved, but leakage current increases
Solution Approach 1:
The air-gap spacer serves as an insulating intermediary between closely spaced conductive patterns, preventing direct electrical contact and reducing leakage current paths while maintaining high integration density through reduced spacing.
Solution Approach 2:
Air is extracted or removed from the space between conductive patterns to create a controlled air-gap, eliminating the parasitic capacitance and leakage pathways that would exist with traditional dielectric materials or direct contact.
3Object-generated harmful factors
If air-gap spacers are formed between conductive patterns, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The air-gap spacer is formed using a self-aligned process where the spacer material automatically positions itself relative to the conductive patterns through conformal deposition and anisotropic etching. This self-service approach reduces the need for additional alignment steps and simplifies the overall manufacturing process despite the added structural element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic capacitance and leakage current, enhancing the operating performance and reliability of the integrated circuit devices by creating a space between conductive elements.
Implementation Method 1
The upper conductive pattern may expose a portion of an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern, an inner sidewall of one of the pair of spacers, the portion of the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern define a space. The capping pattern may seal a top portion of the space such that a cavity may be disposed under the capping pattern. In various embodiments, the cavity may include an air-gap.
Data Source
AI summary
Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.