Air Gap Spacer Structure for DRAM Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor devices, particularly dynamic random access memories (DRAMs), become more highly integrated and miniaturized, the design rules change, leading to challenges in reducing parasitic capacitance and ensuring operational stability due to the need for enlarged connection margins between bit line contacts and landing pads, while existing technologies face difficulties in forming air gap spacers effectively.
Innovation Solution
The semiconductor device incorporates a structure with air gap spacers between bit lines and contact plugs, featuring a blocking insulating layer and an air gap capping layer, along with partial layers that surround and connect the air gap spacers, using silicon nitride and silicon oxide materials to reduce parasitic capacitance and enhance operational stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If air gap spacers are introduced to reduce parasitic capacitance, then operational stability is improved, but device complexity increases due to additional blocking insulating layers and capping layers
Solution Approach 1:
The air gap spacer structure is segmented into multiple functional layers: a blocking insulating layer at the bottom to prevent shorting, an air gap spacer body for capacitance reduction, and an air gap capping layer at the top for protection. This segmentation allows each layer to perform its specific function optimally while collectively achieving both reliability improvement and controlled complexity.
Solution Approach 2:
The blocking insulating layer acts as an intermediary between the semiconductor substrate and the air gap spacer, preventing direct contact that would cause shorting. The air gap capping layer serves as an intermediary protecting the air gap spacer from damage. These intermediary layers enable the air gap spacer to function effectively without introducing excessive complexity.
2Productivity
If design rules are changed to accommodate miniaturization, then device integration is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent changes the physical parameters of the spacer structure by introducing air gaps (changing dielectric constant) and controlling the heights of different layers relative to each other. The blocking insulating layer height is controlled to be less than the air gap spacer height, while the capping layer extends beyond. These parameter changes enable miniaturization while maintaining manufacturability through standard deposition and etching processes.
3Reliability
If connection margins are enlarged between bit line contacts and landing pads, then reliability is improved, but area occupied increases
Solution Approach 1:
The patent uses air (a porous vacuum material) as the dielectric in the air gap spacer structure. This allows for effective electrical isolation and improved connection margins between bit line contacts and landing pads without requiring additional physical space, as air gaps provide high capacitance reduction per unit volume compared to solid dielectric materials.
Data Source
AI summary
A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region; a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug; a first air gap spacer between the first contact plug and the bit line; a landing pad on the first contact plug; a blocking insulating layer on the bit line; and an air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad, an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad.