Air-Gap Spacer for DRAM Bit Line RC Delay
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Solution Overview
Problem
The scaling down of DRAM cell size leads to increased line resistance and parasitic capacitance, resulting in RC delay issues and potential collapse due to limitations in fabrication technologies, necessitating an improved memory cell structure with a buried gate.
Innovation Solution
An air-gap layer is formed between bit lines and storage node contacts using a tri-layered spacer etching process, which reduces line resistance and parasitic capacitance while providing better structural support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the line width is reduced to increase integration level, then the memory capacity is improved, but the line resistance increases
Solution Approach 1:
The patent changes the physical state of the spacer material from solid to air-gap by selective removal, thereby changing the electrical parameters (dielectric constant and resistance) of the structure. This allows reduced line resistance while maintaining the scaled-down geometry for high memory capacity.
Solution Approach 2:
The patent introduces air-gaps (porous structure) between the bit line and storage node contact. These air-gaps have lower dielectric constant compared to solid materials, reducing parasitic capacitance and improving RC delay performance while enabling continued scaling for higher memory capacity.
2Productivity
If the space between wires is shrunk to increase integration level, then the memory capacity is improved, but the parasitic capacitance increases
Solution Approach 1:
The patent introduces air-gaps (porous structure) between the bit line and storage node contact. These air-gaps have lower dielectric constant compared to solid materials, reducing parasitic capacitance and improving RC delay performance while enabling continued scaling for higher memory capacity.
Solution Approach 2:
The patent changes the physical state of the spacer material from solid to air-gap by selective removal, thereby changing the electrical parameters (dielectric constant and capacitance) of the structure. This allows reduced parasitic capacitance while maintaining the shrunk spacing for high memory capacity.
3Reliability
If the air-gap layer is formed to reduce RC delay, then the electrical performance is improved, but the structural support is weakened
Solution Approach 1:
The patent segments the air-gap formation process into two distinct stages: first forming air-gaps at the bit line interface, then forming air-gaps at the storage node contact interface. This segmentation allows optimized electrical performance at each interface while maintaining structural support through the tri-layered spacer architecture.
Solution Approach 2:
The patent extends air-gap formation to multiple dimensions and interfaces: between bit line and storage node contact, and between storage node contact and pad. This multi-dimensional approach optimizes RC delay at each interface while the tri-layered spacer structure provides structural support across all dimensions.
4Reliability
If the tri-layered spacer is used to form air-gaps, then the RC delay is reduced, but the process complexity increases
Solution Approach 1:
The patent segments the air-gap formation process into two distinct stages: first forming air-gaps at the bit line interface, then forming air-gaps at the storage node contact interface. This segmentation allows optimized electrical performance at each interface while managing process complexity through systematic, step-by-step fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air-gap layer effectively addresses RC delay issues and prevents collapse by lowering dielectric constant and enhancing structural integrity, thereby improving the performance and reliability of DRAM devices.
Implementation Method 1
The air-gap layer is able to improve the aforementioned RC delay issues... lowering dielectric constant and enhancing structural integrity
Implementation Method 2
the semiconductor memory device may further improve the possible collapse issues caused by the poor supporting of the air-gap layer
Data Source
AI summary
A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.