Air-Gap Spacer Gate Contact Over Active Area
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Solution Overview
Problem
Conventional semiconductor device fabrication strategies face challenges in downward scaling due to incompatibility between air-gap spacers and gate contact placement over the active area, leading to potential interactions and electrical shorts.
Innovation Solution
A method is developed to fabricate transistors with air-gap spacers surrounded by the same spacer material on opposite sidewalls of the gate electrode, along with lower and upper gate contacts, ensuring that the upper gate contact is situated above the active region without electrical interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If air-gap spacers are used to reduce capacitance, then device performance is improved, but compatibility with gate contact over active area is lost due to potential electrical shorts
Solution Approach 1:
The patent introduces a vertical stacking arrangement where the gate contact is positioned above the air-gap spacer in the vertical dimension rather than having them coexist at the same lateral level. This dimensional separation allows both features to coexist without electrical interference, enabling gate contact over active area while maintaining air-gap spacer benefits for capacitance reduction.
Solution Approach 2:
The gate contact structure is nested above the air-gap spacer structure, with the lower gate contact portion positioned within the vertical space above the spacer. This nesting arrangement allows the gate contact to be situated over the active region while the air-gap spacer remains below, preventing electrical shorts while maintaining both functionalities.
2Productivity
If conventional fabrication strategies are used, then manufacturing simplicity is maintained, but downward scaling is limited due to incompatibility between air-gap spacers and gate contact placement
Solution Approach 1:
The gate contact is divided into multiple portions (lower gate contact portion and upper gate contact portion) that are formed at different stages of fabrication. The lower portion is formed before the air-gap spacer, while the upper portion is formed after. This segmentation allows each component to be fabricated independently without interfering with the other, enabling downward scaling while managing fabrication complexity.
Solution Approach 2:
The lower gate contact portion is formed in advance before the air-gap spacer is created. This preliminary action establishes the foundation for subsequent spacer formation and upper gate contact creation, allowing the fabrication process to proceed in a structured sequence that accommodates both features without requiring complete process redesign.
3Length of moving object
If gate contact is placed over active area for downward scaling, then device size is reduced, but electrical shorts with air-gap spacers may occur
Solution Approach 1:
By positioning the gate contact vertically above the air-gap spacer rather than laterally adjacent, the patent eliminates the risk of electrical shorts while maintaining the compact footprint. The vertical separation in the z-dimension provides electrical isolation while allowing the gate contact to overlie the active region for continued downward scaling.
Solution Approach 2:
The air-gap spacer structure serves as an intermediary element that is vertically positioned below the gate contact. This intermediary arrangement provides electrical isolation between the gate contact and underlying structures while allowing the gate contact to be positioned over the active region, preventing shorts while maintaining scaling benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables favorable downward scaling of semiconductor devices by reducing capacitance and preventing electrical shorts, allowing for increased performance and compatibility between air-gap spacers and gate contacts.
Implementation Method 1
air-gap spacers (low-k) provide a capacitance reduction over conventional spacers, leading to increased performance
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.