Air Gap Spacer Formation for Transistor Miller Capacitance Reduction
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Solution Overview
Problem
As transistor dimensions shrink, parasitic parameters such as miller capacitance adversely affect device performance, and existing spacer materials like silicon nitride hinder the reduction of miller capacitance while limiting process flow in complex transistor formation.
Innovation Solution
Forming an air gap between the gate electrode and source/drain contact by depositing a low-K dielectric material under controlled conditions, such as using carbon doped silicon dioxide, to reduce the combined dielectric constant and thereby decrease miller capacitance, while maintaining process flow efficiency by initially using silicon nitride sidewall spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon nitride is used as sidewall spacer, then process flow for complex transistors is maintained, but miller capacitance cannot be reduced
Solution Approach 1:
The spacer structure is segmented into two distinct materials: silicon nitride for the sidewall spacer (maintaining process flow) and oxide for the inter-level dielectric (enabling capacitance reduction). This segmentation allows each material to fulfill its specific function optimally without compromise.
Solution Approach 2:
Different dielectric materials are applied to different locations: silicon nitride is used where process compatibility is needed (sidewall spacer), while oxide is used where low capacitance is needed (inter-level dielectric). This local differentiation resolves the contradiction by optimizing each region for its specific requirement.
2Object-generated harmful factors
If oxide is used as spacer, then miller capacitance is reduced, but process flow for complex transistors is limited
Solution Approach 1:
The dielectric structure is divided into two parts with different materials: oxide for the inter-level dielectric (reducing capacitance) and silicon nitride for the sidewall spacer (enabling complex transistor formation). This segmentation allows both benefits to coexist.
Solution Approach 2:
Oxide is selectively applied to the inter-level dielectric region where low capacitance is critical, while silicon nitride is used in the sidewall spacer region where process compatibility is critical. This localized material selection resolves the contradiction.
3Productivity
If transistor dimensions are shrunk, then device density is increased, but parasitic parameters adversely affect performance
Solution Approach 1:
The air gap introduced in the inter-level dielectric creates a porous/low-density region with effective dielectric constant close to 1, significantly reducing parasitic capacitance in the scaled-down device while maintaining high device density through continued miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces miller capacitance and leakage, improving transistor and circuit performance without impairing the process flow, achieving capacitance values below 0.23 femtoFarads and enhancing overall device efficiency.
Implementation Method 1
depositing a dielectric material under conditions to achieve low step coverage between the gate electrode and source/drain contact to form an air gap
Implementation Method 2
depositing a dielectric material at a deposition rate greater than about 750 nanometers per minute, a pressure greater than about 100 mT, an RF power frequency less than about 25 W, and a temperature less than about 275 C.°
Implementation Method 3
The miller capacitance is heavily dependent upon the dielectric constant of the spacer material. The lower the dielectric constant of the spacer material, the lower the miller capacitance
Implementation Method 4
Nitrides, such as silicon nitride, are conventionally employed as sidewall spacers, and typically have a dielectric constant of about 6 to 7, with the dielectric constant of air being 1
Data Source
AI summary
Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.