Air-Gap Spacer for Vertical FET Parasitic Capacitance
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Solution Overview
Problem
Vertical field effect transistors (VFETs) face challenges in scaling due to parasitic capacitance between adjacent conductive elements, which limits further dimension reduction and performance enhancement.
Innovation Solution
The method involves forming an air-gap spacer by depositing silicon nitride over the gate and epitaxial layer in a VFET structure, creating gaps between the top source/drain region and the gate, which reduces parasitic capacitance and inhibits electrical shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the contact to the bottom source/drain is formed from the top of the structure such that the bottom source/drain contact overlaps the gate, then the contacted gate pitch can be decoupled from the gate length, but this overlapping configuration creates undesired parasitic capacitance between adjacent conductive elements
Solution Approach 1:
The patent segments the conductive path by introducing an air gap that divides the overlapping region into separate sections. The air gap spacer physically divides the gate and source/drain contact regions, preventing direct electrical coupling while maintaining the overlapping configuration for pitch decoupling.
Solution Approach 2:
The air gap spacer acts as an intermediary element between the gate and the source/drain contact. This intermediate structure provides physical separation and electrical isolation, eliminating parasitic capacitance while allowing the overlapping configuration to persist for architectural flexibility.
2Length of moving object
If the dimensions of field effect transistor elements are decreased to enable scaling, then smaller device dimensions with less short channel effects are achieved, but parasitic capacitance between adjacent conductive elements increases and limits further dimension reduction
Solution Approach 1:
The patent extracts the harmful parasitic capacitance by removing the direct conductive overlap between gate and source/drain contact. The air gap spacer takes out the problematic electrical coupling while preserving the physical overlapping configuration that enables scaled dimensions.
Solution Approach 2:
The patent changes the electrical parameter (capacitance) by introducing a physical gap that alters the electrical field distribution. This parameter change eliminates parasitic capacitance while maintaining the geometric configuration needed for scaled device dimensions.
3Reliability
If air-gap spacer is formed by depositing silicon nitride over the gate and epitaxial layer, then parasitic capacitance is reduced and electrical shorting is inhibited, but additional manufacturing steps are required
Solution Approach 1:
The air gap spacer is formed preliminarily during the epitaxial growth process rather than as a separate post-processing step. The spacer structure is prepared in advance as part of the standard fabrication sequence, integrating the isolation function into the existing manufacturing flow.
Solution Approach 2:
The epitaxial growth process itself serves to form the air gap spacer structure. The self-aligned nature of the epitaxial process automatically positions the air gap spacer correctly without requiring additional alignment steps or complex patterning operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases parasitic capacitance, allowing for more scalable and high-performance VFET designs by creating air gaps that reduce electrical interference between the gate and the top source/drain region.
Implementation Method 1
depositing SiN (silicon nitride) to form the air-gap spacer adjacent the epitaxial layer and the top region of the fin
Data Source
AI summary
A method is presented for forming a semiconductor structure. The method includes forming a fin over a bottom source/drain region, forming a high-k metal gate (HKMG) adjacent the fin, forming an epitaxial layer over the fin such that at least one gap region is defined adjacent the HKMG, and forming a top source/drain region over the epitaxial layer and the at least one gap region. A hard mask is deposited before the epitaxial layer to cover the fin and the HKMG. An inter-level dielectric (ILD) oxide is deposited adjacent the hard mask. The hard mask is etched to expose a top region of the fin to receive the epitaxial layer. At least one gap region is defined adjacent top sidewalls of the fin.