Air Gap Transistor Bulk Substrate Junction Capacitance
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Solution Overview
Problem
Bulk semiconductor substrates have higher n-type field effect transistor (NFET) off capacitance due to larger source/drain junction areas, which is 30% higher than semiconductor-on-insulator (SOI) substrates, and introducing an air gap under the channel region increases threshold voltage variability and mechanical stress.
Innovation Solution
A transistor design with air gaps under the source/drain regions but not under the channel region, utilizing a bulk semiconductor substrate, which reduces junction capacitance to near SOI levels without the disadvantages of air gaps under the channel region, and includes a doped polysilicon isolation region and trench isolation to enhance electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If air gap is positioned under channel region to improve bulk semiconductor substrate performance, then junction capacitance is reduced, but threshold voltage variability increases and mechanical stress is created
Solution Approach 1:
The patent applies local quality by positioning air gaps selectively under the source and drain regions while explicitly excluding the channel region. This localized approach reduces junction capacitance at the source/drain interfaces without introducing the harmful effects (threshold voltage variability and mechanical stress) that occur when air gaps are placed under the channel region. The air gaps are confined to specific locations where they provide capacitance reduction benefit without compromising transistor reliability.
2Loss of energy
If air gap is positioned under channel region to reduce junction capacitance, then capacitance is reduced, but mechanical stress is created on channel region
Solution Approach 1:
The patent implements local quality by restricting air gap placement to the source and drain regions only, with explicit exclusion of the channel region. This spatial differentiation allows the air gaps to reduce junction capacitance where needed at the source/drain interfaces while preventing mechanical stress from being introduced into the channel region, thereby avoiding the trade-off between capacitance reduction and mechanical integrity.
3Ease of manufacture
If bulk semiconductor substrate is used instead of SOI substrate, then manufacturing cost is reduced, but off capacitance is 30% higher
Solution Approach 1:
The patent applies parameter changes by modifying the physical structure of the bulk semiconductor substrate through the introduction of air gaps under the source and drain regions. This structural parameter change reduces the junction capacitance of the bulk substrate, bringing it down to levels comparable to SOI substrates. The air gaps alter the electrical parameters (capacitance) without changing the fundamental substrate type, thereby maintaining the cost advantage of bulk substrates while achieving the performance characteristics of SOI substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gaps reduce off capacitance by up to 25% to match SOI substrate levels, improving transistor performance without mechanical stress, and the doped polysilicon isolation region provides high resistivity for effective electrical insulation.
Implementation Method 1
an air gap under source/drain regions in a bulk semiconductor substrate to reduce junction capacitance to near semiconductor-on-insulator (SOI) substrate levels
Implementation Method 2
a doped polysilicon isolation region in the bulk semiconductor substrate extending below the trench isolation and under the gate, the first source/drain region and the second source/drain region
Data Source
AI summary
A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.