Air-Gap Wiring Void Formation Inhibition for Timing Optimization
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Solution Overview
Problem
Existing methods for optimizing semiconductor integrated circuit device timing face challenges such as increased design periods due to backtracking in logic re-synthesis and function re-verification, and the Air-Gap technology leads to parasitic capacitance increases when wiring distances exceed specified spacings, complicating manufacturing processes and increasing costs and time-to-market.
Innovation Solution
A manufacturing method that involves determining timing constraint violations and setting up void formation inhibition zones between adjacent wirings to control parasitic capacitance, allowing for timing optimization without adding complexity to the manufacturing process or increasing costs, by inhibiting void formation in specific zones and forming voids outside them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the distance between adjacent wirings is increased to reduce parasitic capacitance, then wiring RC delay is reduced, but wiring pitch becomes insufficient and wiring channels are wasted
Solution Approach 1:
The patent applies Air-Gap technology to create void spaces between adjacent wirings, effectively introducing a porous structure into the wiring layout. This reduces parasitic capacitance between wirings without increasing the overall wiring pitch, as the voids occupy space that would otherwise be filled with insulating material. The selective formation of Air-Gaps in specific regions allows for RC delay reduction while maintaining efficient wiring channel utilization.
2Loss of energy
If Air-Gap is formed between all adjacent wirings to reduce parasitic capacitance, then wiring RC delay is reduced, but parasitic capacitance increases in regions where wiring distance exceeds specified spacing
Solution Approach 1:
The patent implements selective Air-Gap formation based on local wiring characteristics. Air-Gaps are formed only in regions where the distance between adjacent wirings is within a specified threshold, while regions with larger spacing are excluded from Air-Gap formation. This local differentiation ensures that parasitic capacitance is reduced where needed without causing unwanted capacitance increases in regions where wiring distance already exceeds specification, thereby achieving precise parasitic capacitance control.
Solution Approach 2:
The patent employs a feedback mechanism by calculating and comparing the actual distance between adjacent wirings against a predetermined specification before deciding whether to form Air-Gaps. This distance-based feedback control ensures that Air-Gap formation occurs only in appropriate regions, preventing the parasitic capacitance increase problem that would occur in regions with excessive wiring spacing.
3Loss of time
If conventional timing optimization methods are used such as logic re-synthesis, then timing constraints can be adjusted, but design period is increased due to back tracking
Solution Approach 1:
The patent changes the physical parameter of parasitic capacitance by selectively forming Air-Gaps between adjacent wirings, rather than changing logic structure through re-synthesis. This physical parameter modification directly affects signal propagation delay without requiring iterative logic design modifications, thereby reducing the design period while achieving timing constraint optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables timing optimization in semiconductor integrated circuit devices without increasing manufacturing process complexity, costs, or time-to-market, by effectively managing parasitic capacitance and reducing wiring RC delay.
Implementation Method 1
parasitic capacitance reduction between wirings by means of development of lower dielectric constant (low-k) materials for an insulating film between wiring layers
Implementation Method 2
a void (Air-Gap) is formed between adjacent wirings close to each other within a specified spacing
Data Source
AI summary
Provided is a method for manufacturing a semiconductor integrated circuit device which enables a timing optimization without giving additions to a manufacturing process and increasing cost and TAT. Existence of a timing constraint violation is determined, and when a timing constraint violation is detected, to dissolve the violation, a void formation inhibition zone is set up in a part or all of a spacing (inter-wiring spacing) between an optimization-target wiring which needs a further delay time of a signal and clock and an adjacent wiring adjacent to the optimization-target wiring having a spacing within a specified wiring spacing, and an insulating film is formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring in the void formation inhibition zone, and voids are formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring outside the void formation inhibition zone.