Air-Gapped Isolation Walls for Dense FinFET and GAA Gate Cuts
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Solution Overview
Problem
Conventional transistors face issues with parasitic capacitance due to tightly-spaced conductive features and power delivery vias, which degrade device performance and increase density on IC chips, particularly in non-planar transistors like FinFETs and GAA transistors.
Innovation Solution
Incorporation of air gaps between conductive components in the transistor layer, formed by etching and recessing oxide layers to ensure adequate capping, reducing parasitic capacitance and enhancing electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conductive features are tightly-spaced to increase density, then device density is improved, but parasitic capacitance increases and performance degrades
Solution Approach 1:
Air gaps are introduced as intermediary structures between adjacent conductive features (gates, vias, and interconnects). These air gaps act as mediators that reduce parasitic capacitance while allowing conductive features to remain tightly-spaced for high density. The air gap serves as a low-dielectric-constant material that minimizes unwanted capacitive coupling between neighboring conductors.
Solution Approach 2:
Air gaps are selectively placed in specific locations where parasitic capacitance is most problematic, such as between adjacent gates, between vias and gates, and between interconnect lines. This local application of air gaps allows high density to be maintained in regions where capacitance is less critical while reducing parasitic effects in sensitive areas.
2Object-generated harmful factors
If air gaps are formed by etching oxide layers, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
Oxide layers are deposited and patterned in advance to define the locations where air gaps will subsequently be formed. This preliminary oxide structure serves as a template that guides the etching process, ensuring that air gaps are created at the correct positions with appropriate dimensions. The oxide layer is removed after serving its purpose as a structural guide.
Solution Approach 2:
The oxide layer is temporarily introduced to define air gap locations, then selectively removed to create the air gaps. The oxide material is discarded after fulfilling its role as a patterning template, and the air gap space is recovered as the functional feature that reduces parasitic capacitance.
3Reliability
If oxide layers are recessed to expose via ends, then adequate capping is ensured, but manufacturing precision requirements increase
Solution Approach 1:
The recessing process is controlled to expose the ends of vias at a specific depth, creating a feedback mechanism where the via end itself serves as the termination point for the oxide removal. This self-regulating approach ensures that the oxide is recessed to the correct depth without requiring external measurement or complex control systems.
Solution Approach 2:
The via structure itself serves the dual function of both electrical connection and depth reference for the oxide recessing process. The via end automatically defines when the recessing should stop, eliminating the need for separate depth measurement or control mechanisms.
Data Source
AI summary
Air gaps are incorporated into a transistor layer to reduce capacitance between conductive components. In some embodiments, along a gate cut region extending across the gates of multiple transistors, a gate cut dielectric may be partially or fully replaced by an air gap. The air gap may extend between two adjacent gates of two adjacent transistors, or between a gate and a via, where the via extends through the gate line and between two gates. The air gaps are capped by a dielectric material, so that additional layers (e.g., back side interconnect layers) may be formed over the air gap. An oxide layer over the transistor layer may be recessed relative to a via to ensure capping of the air gaps. The air gaps may be widened outward from a central seam in the gate cute dielectric.