Air Gaps Between Bit Lines in 3D NAND Memory
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Solution Overview
Problem
Current semiconductor devices face challenges in effectively forming air gaps between bit lines, which are crucial for improving device performance and density, especially in three-dimensional NAND memory structures.
Innovation Solution
A semiconductor structure is formed with bit lines separated by air gaps, achieved by creating a capping-level material layer with cavity-containing openings and protruding portions, and using a method that involves forming a via-level dielectric material layer and conductive via structures to expose the bit-line-level sacrificial fill layer, followed by removing the sacrificial fill material to create the air gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If air gaps are formed between bit lines to improve device performance and density, then electrical resistance is reduced and storage capacity is increased, but the manufacturing complexity and difficulty of forming precise air gaps increases
Solution Approach 1:
A sacrificial fill layer is deposited between the bit lines before the air gaps are formed. This preliminary placement of removable material provides a template for the air gap formation process, enabling precise control over gap location and dimensions while simplifying the overall manufacturing sequence
Solution Approach 2:
The sacrificial fill layer acts as an intermediary material that temporarily occupies the space where air gaps will eventually form. This mediator material facilitates the creation of well-defined air gaps through subsequent removal processes, transforming a complex direct air gap formation into a controlled multi-step process
2Quantity of substance
If air gaps are formed between bit lines to increase storage capacity, then device density is improved, but the manufacturing precision required to form uniform air gaps increases
Solution Approach 1:
The sacrificial fill layer is selectively deposited only in specific regions between the bit lines where air gaps are desired. This localized placement ensures that air gaps form only in the intended locations with consistent dimensions, achieving uniformity across the device structure
Solution Approach 2:
The thickness and material properties of the sacrificial fill layer are carefully controlled during deposition to ensure uniform air gap formation. By adjusting deposition parameters such as film thickness and material composition, precise control over the final air gap dimensions is achieved
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient air gaps between bit lines, enhancing the performance and density of semiconductor devices, particularly in three-dimensional NAND memory structures by reducing electrical resistance and increasing storage capacity.
Implementation Method 1
removing the bit-line-level sacrificial fill layer by introducing an etchant through the openings that removes the sacrificial fill material to form air gaps between the bit lines
Data Source
AI summary
A semiconductor structure includes a semiconductor device, bit lines electrically connected to the semiconductor device, air gaps located between the bit lines, a capping-level material layer, a via-level dielectric material layer located between the bit lines and the capping-level material layer, and conductive via structures extending through the via-level dielectric material layer and contacting a top surface of a respective one of the bit lines. The capping-level material layer contains cavity-containing openings exposing the air gaps. The capping-level material layer contains protruding portions that extend into peripheral regions of the cavity-containing openings.