Air Gaps Between Conductive Features in Semiconductor Memory
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Solution Overview
Problem
High integration density in semiconductor devices leads to reduced reliability due to increased capacitive coupling between conductive features, resulting in higher power consumption and RC delay.
Innovation Solution
Incorporating air gaps between conductive features and using a work-function adjustment layer with a low work function to minimize gate-induced drain leakage current and adjust the work function of the upper electrode structure, while forming a semiconductor memory device with isolation layers and doped regions in a substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high integration density is implemented to increase device functionality, then device complexity and functionality are improved, but capacitive coupling between conductive features increases leading to reduced reliability and higher power consumption
Solution Approach 1:
The patent divides the continuous conductive structure into segmented sections separated by air gaps. The air gap isolation structure segments the conductive features, reducing parasitic capacitance between adjacent conductors while maintaining high integration density and device functionality.
Solution Approach 2:
The patent extracts the dielectric material between conductive features and replaces it with air gaps. This removal of material creates isolated conductive sections, reducing capacitive coupling and improving device reliability without sacrificing integration density.
2Adaptability or versatility
If high integration density is implemented, then device functionality is improved, but power consumption increases due to increased capacitive coupling
Solution Approach 1:
The air gap isolation segments conductive features into isolated sections, reducing parasitic capacitance. This segmentation decreases the energy required for signal transitions and reduces overall power consumption while maintaining high device functionality.
Solution Approach 2:
The patent changes the dielectric parameter between conductive features from solid dielectric material to air (with lower permittivity). This parameter change reduces capacitive coupling and the associated power consumption while preserving device functionality.
3Reliability
If air gaps are introduced between conductive features, then parasitic capacitance is reduced improving reliability, but device complexity increases
Solution Approach 1:
The air gap acts as an intermediary isolation structure between conductive features. This intermediary element reduces parasitic capacitance and improves reliability while the self-aligned formation process keeps the manufacturing complexity manageable.
4Reliability
If work-function adjustment layer is added to minimize gate-induced drain leakage, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The work-function adjustment layer is formed preliminarily during the electrode structure fabrication process. This preliminary action adjusts the work function to minimize gate-induced drain leakage before subsequent processing steps, improving device performance while integrating the function into the existing manufacturing flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces parasitic capacitance, decreases power consumption, and enhances overall device performance by minimizing gate-induced drain leakage current and adjusting the work function of the upper electrode structure, thereby increasing the yield rate of semiconductor devices.
Implementation Method 1
reduces parasitic capacitance, decreases power consumption
Implementation Method 2
using a work-function adjustment layer with a low work function to minimize gate-induced drain leakage current and adjust the work function of the upper electrode structure
Data Source
AI summary
The present disclosure provides a method for preparing a semiconductor memory device with air gaps between conductive features. The method includes forming an isolation layer defining a first active region in a substrate; forming a first doped region in the first active region; forming a first word line buried in a first trench adjacent to the first doped region; and forming a high-level bit line contact positioned on the first doped region; forming a first air gap surrounding the high-level bit line contact. The forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure. The forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer; and forming a work-function adjustment layer disposed between the source layer and the conductive layer.