Air Gaps Between Conductive Lines in Vertical Memory Stacks
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Solution Overview
Problem
Current vertical memory structures face challenges in increasing capacity and density due to high-aspect-ratio etching requirements, which lead to tapered channel bores and increased capacitance, limiting the number of layers to around 64.
Innovation Solution
Introducing voids or air gaps between conductive lines with a lower dielectric constant, such as air or low-κ materials, to reduce capacitance and enable further scaling without increasing the overall size of the memory structure, allowing for more layers, up to 128 or more.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-aspect-ratio etching is used to increase the number of layers, then memory density is improved, but capacitance increases and manufacturing precision deteriorates
Solution Approach 1:
The patent changes the dielectric parameter (dielectric constant) of the material between conductive lines from high-k materials to low-k materials or air gaps. This parameter change reduces capacitance between adjacent conductive lines, enabling increased memory density without the capacitance penalty that normally accompanies higher layer counts.
2Quantity of substance
If high-aspect-ratio etching is used to increase the number of layers, then memory density is improved, but manufacturing precision deteriorates due to tapered channel bores
Solution Approach 1:
The patent introduces voids or air gaps between conductive lines, which changes the physical and chemical parameters of the etching environment. This modification to the etch profile helps maintain uniform channel bore geometry even at high aspect ratios, thereby preserving manufacturing precision while enabling increased memory density.
3Strength
If traditional insulating material is used between conductive lines, then structural integrity is maintained, but capacitance increases limiting scaling
Solution Approach 1:
The patent employs porous low-k dielectric materials or air gaps (voids) between conductive lines. These porous structures have lower dielectric constants than traditional solid insulators, reducing capacitance while still providing adequate structural support. This enables further memory scaling by reducing the electrical interference that normally limits the number of stacked layers.
Solution Approach 2:
The patent extracts or removes portions of the traditional insulating material to create voids or air gaps between conductive lines. By taking out the high-k material and replacing it with low-k material or vacuum, the capacitance is reduced, enabling increased memory density and scaling without compromising the overall structural integrity of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitance, enabling faster memory access, lower power consumption, and increased memory bits per wordline, while maintaining performance, thus overcoming the limitations of traditional vertical memory structures.
Implementation Method 1
Introducing voids or air gaps between conductive lines with a lower dielectric constant, such as air or low-κ materials, to reduce capacitance
Data Source
AI summary
A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.