Air Gaps Between Conductive Pillars Reduce Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices, such as DRAM, are scaled down, the increased parasitic capacitance between adjacent memory cells limits the operation speed due to reduced space between memory cells, leading to greater resistance-capacitance (RC) delay.
Innovation Solution
The manufacturing method involves forming conductive pillars and landing pads with air gaps between them, where the landing pads have a larger footprint than the conductive pillars, allowing air gaps to be formed between adjacent conductive pillars, reducing parasitic capacitance by using a dielectric layer that surrounds the conductive pillars and landing pads, and ensuring electrical connection through capacitor plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory cells are scaled down to reduce device size, then device density is improved, but parasitic capacitance between adjacent memory cells increases
Solution Approach 1:
A dielectric layer is introduced as an intermediary material between adjacent conductive pillars. This dielectric layer acts as a mediator that reduces the capacitive coupling between neighboring conductive structures, thereby lowering parasitic capacitance while maintaining the scaled-down device geometry and high density.
Solution Approach 2:
The dielectric constant of the material between conductive pillars is changed by using a low-k dielectric layer. This parameter change in the dielectric constant directly reduces the parasitic capacitance between adjacent conductive structures, allowing the device to maintain high density with reduced RC delay.
2Area of moving object
If space between memory cells is reduced to increase density, then device size is improved, but operation speed deteriorates due to increased RC delay
Solution Approach 1:
The dielectric layer serves as an intermediary that reduces capacitive coupling between adjacent conductive pillars. By lowering the parasitic capacitance, the RC delay is reduced, which improves signal propagation speed and allows the device to operate faster despite the reduced cell spacing.
Solution Approach 2:
Changing the dielectric constant parameter of the material between conductive structures directly impacts the capacitance value. Using a low-k dielectric reduces the capacitance, thereby reducing the RC time constant and improving operation speed while maintaining high device density.
3Area of moving object
If conductive pillars are placed closer together to increase density, then device area is improved, but parasitic capacitance increases
Solution Approach 1:
The dielectric layer is placed as an intermediary between closely spaced conductive pillars. This intermediary material with low dielectric constant reduces the electric field coupling between adjacent pillars, thereby reducing parasitic capacitance even when the pillars are positioned close together for high density.
Solution Approach 2:
The dielectric layer provides localized quality improvement at the interfaces between conductive pillars. By specifically targeting the regions where parasitic capacitance occurs and applying a low-k dielectric material locally, the patent reduces capacitance at critical locations without affecting the overall device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The formation of air gaps between conductive pillars lowers parasitic capacitance, effectively reducing RC delay and improving the operation speed of the memory device.
Implementation Method 1
forming a dielectric layer to laterally surround the conductive pillar and the landing pad
Data Source
AI summary
The present application provides a memory device with an air gap. The memory device includes an active region disposed in a substrate; a word line disposed in the substrate, wherein the word line is intersected with the active region; a contact structure disposed on the substrate, wherein the contact structure is located at a side of the word line, and electrically connected to the active region; a first conductive layer and a second conductive layer disposed over the substrate, wherein the contact structure is covered by the first and second conductive layers; a conductive pillar overlapped with and electrically connected to the contact structure; a landing pad covers and electrically connects to the conductive pillar, wherein a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad; and a dielectric layer laterally surrounding the conductive pillar and the landing pad.