Air Gaps in Copper Wiring for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional semiconductor devices with copper wiring structures face challenges in reducing parasitic capacitance and capacitance variations, especially as integration density increases, leading to signal delays and crosstalk due to the diffusion of copper into insulating films and variations in etching depths.
Innovation Solution
A manufacturing method that involves forming air gaps between copper wirings with a thinner barrier insulating film on the bottom and using a different material for the via interlayer insulating film as an etching stopper to achieve uniform etching depths and reduce capacitance variations, thereby minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier insulating film is formed on the bottom of air gaps to prevent copper diffusion, then copper diffusion into insulating film is suppressed, but parasitic capacitance between wirings is increased
Solution Approach 1:
The patent applies local quality by forming the barrier insulating film only at specific locations where copper diffusion is most critical (at the bottom of air gaps and in regions adjacent to wirings), rather than uniformly across all surfaces. This localized application prevents copper diffusion while minimizing the overall parasitic capacitance introduced by insulating materials.
Solution Approach 2:
The barrier insulating film is segmented into multiple discrete regions rather than forming a continuous layer. The film is formed in the air gaps between wirings and in specific adjacent regions, creating a segmented barrier structure that provides diffusion protection only where needed, thereby reducing total parasitic capacitance compared to a continuous barrier film.
2Object-affected harmful factors
If etching is performed deeper to reduce parasitic capacitance further, then capacitance is reduced, but capacitance variations increase due to depth variations
Solution Approach 1:
The patent applies partial action by forming the barrier insulating film to a depth that is sufficient to achieve the desired capacitance reduction, but not excessively deep. The film is formed in the air gaps and adjacent regions to an optimized depth that balances capacitance reduction with manufacturing precision, avoiding the increased capacitance variations that would result from deeper etching.
3Object-affected harmful factors
If the barrier insulating film is made thinner to reduce parasitic capacitance, then capacitance is reduced, but copper diffusion prevention capability is weakened
Solution Approach 1:
The barrier insulating film is made thinner in specific locations (in the air gaps between wirings and in adjacent regions) where the required barrier thickness can be reduced while still maintaining effective copper diffusion prevention. This localized thinning reduces parasitic capacitance while the film remains sufficiently thick at critical interfaces to prevent copper diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by approximately 30% to 45% compared to conventional methods and achieves an effective dielectric constant suitable for next-generation nodes, while maintaining mechanical strength and reducing crosstalk.
Implementation Method 1
using a different material for the via interlayer insulating film as an etching stopper to achieve uniform etching depths
Implementation Method 2
forming air gaps between copper wirings with a thinner barrier insulating film on the bottom... effectively reduces parasitic capacitance by approximately 30% to 45%
Implementation Method 3
the surface (bottom and side surfaces) of the buried wiring is covered with a thin barrier metal film, thereby suppressing or preventing copper in the buried wiring from being diffused into the insulating film
Data Source
AI summary
Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space is made smaller than that on the wirings, thereby efficiently reducing wiring capacitance of narrow-line pitches. Then, first and second low dielectric constant insulating films are formed. Here, a deposition rate of the first insulating film at an upper portion of the side surfaces of facing wirings is made higher than that at a lower portion thereof, thereby forming air gaps. Finally, the second insulating film is planarized by interlayer CMP.