Air Gaps in Multilayer IC Wiring Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming air gaps in multilayer integrated circuits (ICs) are complex and require alignment with wiring layout rules, making it difficult to achieve a uniform reduction of parasitic capacitance independently of the wiring layout and using conventional photolithography.
Innovation Solution
A cross pattern of air gaps and dielectric stripes of equal widths is created in the wiring layer, orthogonal or diagonal to the wiring direction, with wires replacing portions of the pattern to form a uniform air gap distribution, allowing for easy production by conventional photolithography and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form air gaps by aligning with wiring layout rules, then the air gaps can be formed in the wiring layer, but the process becomes complex and cannot achieve uniform reduction of parasitic capacitance independently of wiring layout
Solution Approach 1:
The air gap pattern is segmented into a regular cross-hatch grid of independent squares, where each square is defined by orthogonal etch lines. This segmentation allows the pattern to be formed by simple orthogonal photolithography steps rather than complex layout-aligned processes, achieving uniform parasitic capacitance reduction across the entire wiring layer independent of wire placement
Solution Approach 2:
The regular cross-hatch air gap pattern serves multiple functions: it provides uniform parasitic capacitance reduction, maintains structural integrity of the dielectric layer, and is compatible with conventional photolithography processes. The pattern is universal in that it can be applied to any wiring layout without requiring alignment to specific wire positions or directions
2Reliability
If air gaps are formed to reduce parasitic capacitance, then signal propagation delay is reduced, but the manufacturing process becomes more complex and difficult to produce with conventional photolithography
Solution Approach 1:
Instead of forming air gaps by directly patterning them to match wiring layouts (complex approach), the invention inverts the approach by forming a universal regular cross-hatch pattern that is independent of wiring layout. This inverted approach uses simple orthogonal etch lines that align with the photolithography grid rather than requiring alignment with complex wire patterns, making the process easier to manufacture while maintaining the benefit of reduced parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a uniform reduction of parasitic capacitance, translating to power savings of approximately 7-15% in multilayer ICs, while maintaining structural integrity and facilitating wiring layout with orthogonal or diagonal patterns.
Implementation Method 1
Upon, for example, low temperature oxidation, the sacrificial material 40 in FIG. 1A forms volatiles, which then diffuse through permeable bridge layer 30 to form air gap 50 of FIG. 1B
Implementation Method 2
the sacrificial material 40 in FIG. 1A forms volatiles, which then diffuse through permeable bridge layer 30 to form air gap 50 of FIG. 1B
Implementation Method 3
The sacrificial material 40 in FIG. 2A is removed via the perforation 70 to form the air gap 80 in FIG. 2B by an aggressive process, for example, plasma-etching by a reactive gas
Data Source
AI summary
A multilayer integrated circuit (IC) including a cross pattern of air gaps in a wiring layer and methods of making the multilayer IC are provided. The patterning of the air gaps is independent of the wiring layout. Patterns of air gaps including: parallel alternating stripes of air gaps and dielectric that are orthogonal to a uni-directional metal wiring layout; parallel alternating stripes of air gaps and dielectric that are diagonal to either a uni- or bi-directional metal wiring layout; and a checkerboard pattern of air gaps and dielectric that crosses either a uni- or bi-directional metal wiring layout are easily formed by conventional photolithography and provide a comparatively uniform reduction in parasitic capacitance between the wires and the surrounding materials, when about one-half of a total length of the metal wiring layout is disposed within the air gaps.