Air Gaps in Interlayer Insulating Layer for Semiconductor Wiring
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Solution Overview
Problem
As semiconductor devices require higher integration levels, reducing parasitic capacitance between wirings becomes essential to achieve high performance and speed, but existing methods face challenges in forming air gaps without damaging the metal wiring.
Innovation Solution
The semiconductor device incorporates air gaps between metal wirings, with a capping layer covering them, where the air gaps are strategically positioned to minimize parasitic capacitance, achieved through advanced patterning technologies like self-aligned double or quadruple patterning processes, ensuring the gaps are formed without damaging the wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If air gaps are formed between metal wirings to reduce parasitic capacitance, then RC delay is reduced and operating speed is improved, but the metal wiring may be damaged during the air gap formation process
Solution Approach 1:
A capping layer is formed over the metal wiring before air gap formation. This preliminary protective action prevents damage to the metal wiring during subsequent air gap etching processes, while still allowing the air gaps to be formed for parasitic capacitance reduction
Solution Approach 2:
The capping layer acts as an intermediary protective element between the etching process and the metal wiring. It shields the wiring from direct exposure to harsh etching conditions while permitting controlled air gap formation through selective etching or sacrificial material removal
2Object-generated harmful factors
If air gaps are formed close to metal wiring sidewalls to maximize capacitance reduction, then parasitic capacitance is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The capping layer is formed in advance with precise thickness control, establishing predetermined spacing between air gaps and metal wiring sidewalls. This preliminary structuring enables accurate air gap positioning without requiring ultra-precise direct placement, as the capping layer serves as a buffer that defines the spacing
Solution Approach 2:
The thickness of the capping layer is controlled within specific ranges (e.g., 50-200 nm) to optimize the balance between air gap proximity for capacitance reduction and manufacturing feasibility. By adjusting this parameter, the design achieves optimal positioning accuracy that is attainable with current fabrication capabilities
Data Source
AI summary
A semiconductor device includes an interlayer insulating layer disposed on a substrate, a first metal wiring and a second metal wiring disposed in the interlayer insulating layer, the first and second wirings spaced apart from each other in a first direction, the first and second wirings extending to a second direction perpendicular to the first direction, an air gap formed in the interlayer insulating layer between the first metal wiring and the second metal wiring, and spaced apart from a sidewall of the first metal wiring and a sidewall of the second metal wiring, and a capping layer disposed on the interlayer insulating layer, the capping layer covering the first metal wiring, the second metal wiring, and the air gap, wherein the air gap is disposed at a first distance from the first metal wiring in the first direction and at a second distance from the second metal wiring in the first direction, and wherein the first and second distances are the same.