Air Gaps Between Gate Structures Reduce Parasitic Capacitance
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Solution Overview
Problem
The increasing parasitic capacitance between adjacent gate structures in semiconductor memory devices due to scaling down efforts degrades the speed and reliability of memory devices, as it leads to variations in threshold voltage and increased dielectric material usage, which is not adequately reduced by previous methods that only partially fill the space between gates with air.
Innovation Solution
The method involves forming substantially rectangular air gaps with uniform width between adjacent gate structures to maximize the air gap volume, using a protection layer and insulation layers to define the air gaps with vertical and horizontal portions of uniform thickness, thereby minimizing parasitic capacitance and its variance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the space between adjacent gate structures is scaled down to increase memory density, then the memory device density is improved, but the parasitic capacitance between adjacent gate structures increases
Solution Approach 1:
The patent extracts the dielectric material from the space between adjacent gate structures and replaces it with air gaps. This removal of the traditional dielectric layer (which has higher permittivity) and substitution with air (lower permittivity) directly reduces the parasitic capacitance between adjacent gates while maintaining the scaled-down geometry for high density
Solution Approach 2:
The patent changes the dielectric parameter (permittivity) of the material between adjacent gate structures from a high-permittivity dielectric material to air (low permittivity). This parameter change reduces the capacitance value C = εA/d, where ε is the permittivity, thereby reducing parasitic capacitance while maintaining the small spacing for high density
2Object-generated harmful factors
If the dielectric material between adjacent gate structures is reduced, then the parasitic capacitance is decreased, but the threshold voltage variation increases
Solution Approach 1:
The patent applies local quality by creating uniform air gaps with controlled dimensions between adjacent gate structures. The air gaps are formed with specific geometric characteristics (width, height, and uniform distribution) that locally modify the electric field distribution, thereby reducing parasitic capacitance while maintaining consistent threshold voltage across all memory cells
Solution Approach 2:
The patent removes the dielectric material partially (only from the critical regions between adjacent gates) rather than completely, and replaces it with air gaps of optimized dimensions. This partial removal and controlled replacement achieves sufficient parasitic capacitance reduction while maintaining the structural integrity and electrical performance needed for consistent threshold voltage
3Object-generated harmful factors
If air gaps are formed between adjacent gate structures, then the parasitic capacitance is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary action by forming the air gaps between adjacent gate structures during the gate formation process itself, rather than as a separate subsequent step. The air gaps are created as the gates are being patterned and formed, utilizing the same lithography and etching processes, thereby integrating the air gap formation into the existing manufacturing flow without adding significant process complexity
Data Source
AI summary
Methods for forming semiconductor memory structures including a gap between adjacent gate structures are provided. The methods may include forming an insulation layer between the adjacent gate structures. In some embodiments, the methods may include subsequently removing a portion of the insulation layer to leave the gap between the adjacent gate structures.