Air Spacer Integration in Semiconductor FETs
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing parasitic capacitance, which increases power consumption and affects device performance, particularly in planar complementary metal oxide semiconductor field effect transistors (CMOS FETs) due to diffused source/drains inducing capacitance between the source/drain region and the substrate.
Innovation Solution
The introduction of air spacers enclosed by insulating material within the isolation regions under the source/drain diffusion regions, which suppresses junction capacitance, is implemented in the manufacturing process of semiconductor devices, including field effect transistors (FETs), applicable to planar, fin, and gate-all-around FETs. This involves forming spaces under the source/drain regions and filling them with insulating material to create air spacers that reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If diffused source/drain regions are used in planar CMOS FETs, then device manufacturing is simplified, but parasitic capacitance between source/drain and substrate increases
Solution Approach 1:
An embedded insulating layer is introduced as an intermediary between the source/drain diffusion regions and the substrate. This insulating layer acts as a mediator that electrically isolates the source/drain regions from the substrate, thereby reducing parasitic capacitance while maintaining the simplified diffused source/drain structure.
Solution Approach 2:
The harmful capacitive coupling between source/drain and substrate is extracted by removing the direct electrical connection through the substrate. The embedded insulating layer is inserted to break this direct connection, effectively taking out the parasitic capacitance pathway while preserving the diffused source/drain configuration.
2Use of energy by moving object
If parasitic capacitance is reduced to lower power consumption, then energy efficiency improves, but device structure becomes more complex
Solution Approach 1:
The insulating material is applied locally only in the regions where source/drain diffusion regions contact the substrate, rather than throughout the entire device. This localized approach reduces parasitic capacitance at critical interfaces while minimizing the overall structural complexity and material usage.
Solution Approach 2:
The embedded insulating layer is formed preliminarily during the device fabrication process, before final device operation. By incorporating the insulating layer early in the manufacturing sequence, the structure is prepared in advance to minimize parasitic capacitance, enabling lower power consumption without requiring additional complex modifications later.
Data Source
AI summary
In a method of manufacturing a semiconductor device including a field effect transistor (FET), a sacrificial region is formed in a substrate, and a trench is formed in the substrate. A part of the sacrificial region is exposed in the trench. A space is formed by at least partially etching the sacrificial region, an isolation insulating layer is formed in the trench and the space, and a gate structure and a source/drain region are formed. An air spacer is formed in the space under the source/drain region.