Air Spacer Structure in FETs for Lower Parasitic Capacitance
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Solution Overview
Problem
Current materials are insufficient in reducing parasitic capacitance in advanced technology nodes of semiconductor devices, particularly in field-effect transistors, such as planar FETs, FinFETs, and gate-all-around devices, due to limitations in dielectric materials used in middle-end-of-line capacitance reduction.
Innovation Solution
The implementation of an air spacer by using a removable metal gate hard mask liner, which replaces traditional dielectric materials, and the option to replace the metal gate hard mask after source/drain contact metal filling, is introduced to reduce parasitic capacitance in FinFET and GAAFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional dielectric materials are used in middle-end-of-line capacitance reduction, then manufacturing process is simpler, but parasitic capacitance cannot be reduced sufficiently in advanced technology nodes
Solution Approach 1:
The patent changes the dielectric parameter from traditional solid dielectric materials to air (vacuum) as the spacer material. This parameter change reduces the dielectric constant from typical values of 3.9-4.5 (silicon dioxide) to approximately 1.0 (air), thereby significantly reducing parasitic capacitance in the middle-end-of-line region while managing the added process complexity through controlled formation methods.
Solution Approach 2:
The patent introduces a removable metal gate hard mask liner as an intermediary material that enables the formation of air spacers. The liner is deposited conformally, then selectively removed to create air-filled spaces that serve as low-k dielectric regions, effectively mediating between the source/drain contacts and gate structure to reduce capacitance without requiring complex direct air gap formation processes.
2Speed
If air spacer is implemented to reduce parasitic capacitance, then speed performance is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary conformal deposition of the removable metal gate hard mask liner on all surfaces including sidewalls and top surfaces before any air gap formation. This preliminary action ensures uniform coverage and precise thickness control, and the subsequent selective removal creates air spacers with well-defined dimensions, thereby reducing manufacturing precision challenges compared to direct air gap etching methods.
Solution Approach 2:
The conformally deposited removable liner serves multiple functions: it defines the air spacer geometry, protects underlying structures during processing, and self-aligns the air gap formation to the gate and contact structures. This self-service approach reduces the need for additional alignment steps and precision requirements compared to multi-step lithography and etching processes.
Data Source
AI summary
A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.