Air Spacer GAA Semiconductor Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistor features around silicon nanowires in semiconductor manufacturing is challenging, requiring improvements to reduce parasitic capacitance and enhance device performance.
Innovation Solution
The semiconductor structure incorporates air spacers sealed by inner spacers and source/drain features, which are formed through specific etching processes to adjust dimensions and reduce parasitic capacitance, while maintaining the integrity of inner spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If air spacers are formed to reduce parasitic capacitance, then device performance is improved, but spacer integrity may be compromised due to etching processes
Solution Approach 1:
The spacer formation process is segmented into multiple controlled etching steps with intermediate cleaning stages. The first etching step creates initial air gaps, followed by a cleaning step that removes debris, and then a second etching step that completes the air spacer formation. This segmentation allows each step to be optimized independently, reducing cumulative damage to spacer integrity while achieving the desired capacitance reduction.
Solution Approach 2:
A protective layer is deposited on the spacer structures before the etching process begins. This preliminary protective action prevents direct exposure of the spacer material to aggressive etching conditions, maintaining structural integrity while still allowing the etching process to create the necessary air gaps for capacitance reduction.
2Object-affected harmful factors
If aggressive etching is used to create air spacers, then parasitic capacitance is reduced, but manufacturing precision deteriorates due to spacer damage
Solution Approach 1:
The etching process uses periodic alternation between etching and cleaning steps. Each etching cycle creates additional air gaps while the intervening cleaning steps remove etching debris and prevent over-etching. This periodic action enables progressive capacitance reduction with controlled precision, avoiding the cumulative damage that would occur with continuous aggressive etching.
Solution Approach 2:
A sacrificial layer is introduced as an intermediary between the etching process and the spacer structures. This layer absorbs the aggressive etching action, protecting the spacer dimensions while still allowing effective air gap formation. The sacrificial layer is subsequently removed, having served its protective function during the capacitance reduction process.
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes alternatingly stacked first semiconductor layers and second semiconductor layers. The method also includes laterally recessing the first semiconductor layers of the fin structure to form a plurality of notches, forming a plurality of inner spacers in the notches, laterally recessing the inner spacers to form a plurality of recesses in the inner spacers, and growing a source/drain feature over the fin structure. The recesses are sealed by the source/drain feature and the inner spacers to form a plurality of air spacers.