Air Spacer Gate Structure for Collapse-Resistant FinFET Etching
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Solution Overview
Problem
Conventional methods for forming air spacers in semiconductor devices face challenges, particularly in high aspect ratio situations, where gate structures over isolation regions tend to collapse and air spacers are difficult to form efficiently, leading to suboptimal performance in FinFET structures.
Innovation Solution
The formation of a highly etchable liner next to gate spacers in specific regions and selective doping of dielectric gate spacers to enhance etching selectivity, allowing for the efficient creation of air spacers with tunable dimensions and reduced risk of gate structure collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form air spacers, then manufacturing simplicity is maintained, but gate structures over isolation regions collapse and air spacers cannot be formed efficiently
Solution Approach 1:
A sacrificial liner layer is introduced as an intermediary between the gate spacer and the etching process. This liner layer is selectively removed in device regions to enable air spacer formation while being retained in isolation regions to prevent gate structure collapse. The liner acts as a controlled mediator that enables air spacer formation only where needed.
Solution Approach 2:
The liner layer is selectively present or removed in different regions of the substrate. In device regions, the liner is removed to allow air spacer formation, while in isolation regions, the liner is retained to provide structural support. This local differentiation resolves the contradiction by applying different treatments to different spatial locations.
2Reliability
If air spacers are formed with larger dimensions to improve FinFET performance, then device performance improves, but the aspect ratio increases making formation more difficult
Solution Approach 1:
The gate spacer is formed with extended dimensions before the air spacer formation process. By preliminarily creating a larger gate spacer structure, the subsequent air spacer can achieve the desired large dimensions for improved FinFET performance. The preliminary gate spacer structure serves as a template that enables controlled removal to form the final air spacer with optimized dimensions.
Solution Approach 2:
The liner layer serves as a mediator that controls the aspect ratio during air spacer formation. By selectively removing the liner in device regions while retaining it in isolation regions, the process enables formation of air spacers with larger dimensions where needed while maintaining aspect ratio control through the protective liner where structural support is required.
3Productivity
If selective removal of liner and gate spacer is performed to form air spacers, then air spacer formation efficiency improves, but process complexity increases
Solution Approach 1:
The liner layer is designed to be selectively removable through self-aligned etching processes. The liner's material composition and spatial distribution enable automatic differentiation between device regions and isolation regions during etching, without requiring additional masking steps. This self-service approach improves efficiency while minimizing the increase in process complexity.
Solution Approach 2:
The etching process utilizes parameter changes in the liner layer's material properties and spatial distribution to achieve selective removal. By controlling the liner's presence, thickness, or material composition in different regions, the process enables efficient air spacer formation through etching parameter optimization rather than complex procedural steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates the formation of air spacers with optimized dimensions, improving the performance of FinFET structures by reducing the aspect ratio of air spacers and preventing gate structure collapse, while allowing for flexible tuning of air spacer sizes to suit different device regions.
Implementation Method 1
forming a first air spacer in the first device region by removing the liner and the second dielectric spacer
Implementation Method 2
Selective doping of dielectric gate spacers to enhance etching selectivity
Data Source
AI summary
A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.