Air-Spacer MOS Transistor Gate Stack Segmentation
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Solution Overview
Problem
Existing air-spacer MOS transistors face challenges in minimizing stray gate capacitances, particularly at nanometer scales where gate lengths are shorter than 20 nm, leading to significant capacitance values that affect power consumption and switching speed.
Innovation Solution
The design involves a conductive gate stack with a lower portion made of a metal layer and an upper portion made of a doped semiconductor layer, bordered by air spacers and dielectric spacers, where the upper portion's length is decreased to reduce capacitance by increasing the distance between the gate and source/drain contacts, and the gate stack is manufactured using a method that includes forming, etching, and replacing spacers with dielectric and air spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate length is decreased to increase switching speed, then the switching speed is improved, but the gate-source and gate-drain contact capacitances increase significantly
Solution Approach 1:
The gate stack is segmented into two portions with different lengths: a first portion extending over the channel and a second portion that is shorter. This segmentation allows the gate to maintain effective control over the channel while reducing the overlap area with source and drain contacts, thereby decreasing parasitic capacitances and power consumption.
Solution Approach 2:
Different portions of the gate stack are given different local properties: the first portion has full length to ensure proper channel control, while the second portion is shortened to minimize capacitance. This local differentiation optimizes both switching speed and power consumption by addressing different functional requirements in different spatial locations.
2Use of energy by moving object
If air spacers are used to reduce stray capacitances, then the gate-source and gate-drain capacitances are decreased, but the manufacturing complexity increases
Solution Approach 1:
The gate stack is divided into two portions with different lengths, which can be achieved through standard semiconductor manufacturing techniques such as selective etching or deposition. This segmentation approach reduces parasitic capacitances without requiring complex air spacer structures, thereby maintaining manufacturing simplicity while achieving the desired electrical performance.
3Ease of manufacture
If the gate stack length is uniform throughout, then the manufacturing process is simplified, but the gate-source and gate-drain contact capacitances remain high
Solution Approach 1:
The gate stack is segmented into a first portion and a second portion, where the second portion has a shorter length than the first portion. This can be implemented through selective removal or non-uniform deposition techniques that are compatible with existing manufacturing processes. The segmentation reduces the overlap area between the gate and contact regions, thereby decreasing parasitic capacitances and power consumption while maintaining reasonable manufacturing simplicity.
Solution Approach 2:
The gate stack exhibits local quality variation along its length, with the first portion having full length for channel control and the second portion being shortened to reduce capacitance. This local differentiation can be achieved through targeted manufacturing steps that modify only specific regions, balancing manufacturing ease with electrical performance optimization.
Data Source
AI summary
A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.