Air Spacer Structure for Lower Parasitic Capacitance in Semiconductors
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Solution Overview
Problem
Current semiconductor structures face challenges in increasing integration level and reducing parasitic capacitance, particularly between gate and source/drain interconnecting layers, due to limitations in air spacer formation and process window constraints.
Innovation Solution
The semiconductor structure incorporates a design with a first and second spacer, an air gap, and a sealing layer, where the width of the air spacer varies perpendicular to the first spacer, increasing its volume and proportion between the gate and source/drain interconnecting layers, and a method for forming this structure that includes forming a sacrificial spacer with a larger width at the top to facilitate easier removal and enhance process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional air spacer formation process is used, then the manufacturing process is simple, but the process window is narrow and manufacturing precision is poor
Solution Approach 1:
The air spacer structure is segmented into multiple functional layers: a first spacer layer formed on the gate structure sidewall, a second spacer layer formed on the source/drain interconnecting layer sidewall, and a sealing layer. This segmentation allows each layer to be formed with optimized process parameters, improving the overall process window and manufacturing precision while maintaining controllable complexity through modular construction
Solution Approach 2:
The air spacer transitions from a conventional uniform width structure to a tapered structure where the width varies along the vertical dimension. The first spacer has a first width at the gate structure interface and a second width at the sealing layer interface, with the second width being greater than the first width. This dimensional variation increases the process window by providing better etch selectivity and reduces manufacturing precision requirements for individual layers
2Reliability
If the air spacer volume is increased to reduce parasitic capacitance, then semiconductor performance is improved, but the process window for forming the air spacer decreases
Solution Approach 1:
The air spacer exhibits local quality variation with different widths at different vertical positions. The first spacer portion near the gate structure has a narrower width (first width), while the upper portion near the sealing layer has a wider width (second width). This local quality differentiation allows the lower portion to maintain tight process control for proper alignment while the upper portion provides increased volume for parasitic capacitance reduction, effectively decoupling the two requirements
Solution Approach 2:
The air spacer adopts an asymmetric tapered geometry rather than a symmetric uniform structure. The width increases from bottom to top, creating an asymmetric profile that optimizes both the process formation window (easier to form with standard etching processes) and the functional performance (increased volume for capacitance reduction). The asymmetric design naturally provides a larger process window compared to attempting to form a uniformly wide air spacer
3Productivity
If critical dimensions are decreased to increase integration level, then circuit density is improved, but parasitic capacitance between interconnecting structures increases
Solution Approach 1:
The invention utilizes an air-filled spacer structure (pneumatic principle) to provide electrical isolation between the gate structure and source/drain interconnecting layer. The air gap, being a low-dielectric constant medium, effectively reduces parasitic capacitance without occupying significant horizontal space, thus enabling continued scaling for high integration while mitigating the harmful capacitive effects that typically increase as dimensions decrease
Data Source
AI summary
Semiconductor structures and methods for forming the same are provided. One form of a method includes: forming a sidewall structure layer on a sidewall of an interconnecting trench, and forming a source/drain interconnecting layer on a sidewall of the sidewall structure layer, filling the interconnecting trench, and in contact with a source/drain doped region, where the sidewall structure layer includes: a sacrificial spacer, arranged on a sidewall of a first spacer and suspended and spaced apart from the source/drain doped region, where along a direction perpendicular to the sidewall of the first spacer, a width of a part of the sacrificial spacer away from the base is greater than a width of a part of the sacrificial spacer close to the base; and a second spacer, filling a gap between a bottom of the sacrificial spacer and the source/drain doped region and arranged between the sacrificial spacer and the source/drain interconnecting layer; removing the sacrificial spacer to form an air gap defined by the second spacer and the first spacer; and forming a sealing layer sealing a top of the air gap, so that the sealing layer, the first spacer, and the second spacer form an air spacer.