Air Spacer Pinch-Off for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor device dimensions shrink, parasitic capacitance between conductors increases, leading to issues like RC delay, power dissipation, and cross-talk in non-planar transistor architectures such as VFETs, where the parasitic capacitance between a gate and an adjacent contact becomes significant, and between interconnects during BEOL fabrication.
Innovation Solution
The method involves forming a trench between a gate and a contact or between metal interconnects, where a dielectric layer pinches off to trap a pocket of air, creating an air spacer or air gap, which reduces parasitic capacitance by using a combination of dielectric layers and etching processes to expose sidewalls and form conformal or nonconformal dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If device dimensions and component spacing are shrunk to increase device density, then device footprint is reduced, but parasitic capacitance between conductors increases
Solution Approach 1:
The patent extracts the harmful dielectric material from the trench between the gate and contact, replacing it with air (vacuum). This is achieved by forming a trench and then removing the filled dielectric material, creating an air gap that eliminates the parasitic capacitance contribution from the spacer material while maintaining the necessary spacing between components.
Solution Approach 2:
The patent changes the dielectric parameter (permittivity) of the spacer material from a high-value dielectric material to air (permittivity ≈ 1). This parameter change directly reduces the parasitic capacitance between the gate and contact, as capacitance is proportional to the permittivity of the spacer material, while still maintaining the required physical separation.
2Loss of energy
If air gap is formed between gate and contact to reduce parasitic capacitance, then RC delay and power dissipation are reduced, but fabrication process complexity increases
Solution Approach 1:
The patent performs preliminary action by filling the trench with dielectric material before subsequently removing it to create the air gap. This preliminary filling step provides a convenient platform for selective removal processes and ensures proper trench coverage during fabrication, making the overall air gap formation process more controllable and less complex than direct air insertion methods.
Solution Approach 2:
The dielectric material serves as an intermediary during the fabrication process. It is first deposited to fill the trench, providing structural support and process control, and then selectively removed to create the air gap. This intermediary material facilitates the creation of the air gap structure through standard semiconductor fabrication processes rather than requiring direct vacuum formation.
3Speed
If air gap is formed between metal interconnect layers to reduce parasitic capacitance, then signal propagation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-service principles where the air gap structure is created through self-aligned processes. The trench is formed using the metal interconnect structures themselves as alignment references, and the dielectric filling and removal processes are self-aligned to the underlying structures, reducing the need for additional alignment steps and minimizing manufacturing precision requirements.
Solution Approach 2:
The trench formation and dielectric filling are performed as preliminary actions before the final metal interconnect deposition. This preliminary structuring establishes the air gap geometry early in the process, allowing subsequent layers to be deposited conformally over the air gap structure, which maintains the gap integrity and reduces precision requirements for later steps.
Data Source
AI summary
Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.