Air-Replaced Spacer Layout for Lower RC Delay in Self-Aligned Contacts

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing the RC delay of CMOS transistors due to high dielectric capacitance between gate and source/drain structures, which hinders performance improvements in storage capacity and processing speed.

Innovation Solution

The implementation of air-replaced spacers with a low dielectric constant of about 1, formed between the gate structure and self-aligned source/drain contact structures, reduces capacitance by using a dummy silicon spacer and tuning its size, along with a silicon nitride layer to prevent damage and silicide extrusion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional dielectric spacers are used between gate and source/drain structures, then structural support and isolation are provided, but high dielectric capacitance increases RC delay and reduces device performance

Engineering Contradiction:
Improvedevice AC performanceVSAvoidRC delay
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent changes the dielectric constant parameter of the spacer material from conventional high-k dielectric materials to air (k≈1) by removing the spacer material and replacing it with air gaps. This parameter change directly reduces the capacitance between gate and source/drain structures, thereby reducing RC delay and improving device AC performance

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts and removes the conventional dielectric spacer material from between the gate and source/drain structures, replacing it with air gaps. This extraction eliminates the source of high dielectric capacitance while maintaining the necessary structural isolation through alternative means such as self-aligned contact holes

Inventive Principle:
Principle #2Taking out (Extraction)

2Loss of energy

If spacer material is removed to reduce capacitance, then dielectric capacitance decreases and AC performance improves, but structural support and alignment reference are lost

Engineering Contradiction:
Improvedielectric capacitanceVSAvoidself-aligned contact scheme complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements self-aligned contact holes that automatically align with the gate structure without requiring external spacer materials for alignment reference. The contact holes are formed through a self-alignment process where the gate structure itself serves as the alignment reference, eliminating the need for separate spacer components while maintaining manufacturing precision

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent introduces air gaps as an intermediary medium between the gate and source/drain structures. These air gaps serve dual functions: they provide electrical isolation to reduce capacitance while also serving as structural placeholders that maintain the spatial relationships necessary for self-aligned contact formation

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If air gaps are introduced to reduce capacitance, then RC delay decreases and processing speed increases, but manufacturing precision and process control become more difficult

Engineering Contradiction:
Improveprocessing speedVSAvoidair gap formation control
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The manufacturing process uses the gate structure itself as the alignment reference for forming contact holes, eliminating the need for separate spacer materials and their associated alignment steps. This self-alignment approach inherently improves manufacturing precision by using the existing gate dimensions as the control reference, making the air gap formation more controllable and repeatable

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances device AC performance by at least 1.5% compared to CMOS transistors without air-replaced spacers, achieving faster processing speeds and improved storage capacity.

Implementation Method 1

air-replaced spacers with a low dielectric constant of about 1

Methodology Applied
Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS20240339355A1Air-Replaced Spacer for Self-Aligned Contact Scheme
Publication Date: 2024.10.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240339355A1 patent drawing
  • US20240339355A1 patent drawing
  • US20240339355A1 patent drawing

AI summary

The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.