Air Spacer Protection Ring Etching for Low-Capacitance Interconnects
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Solution Overview
Problem
Conventional methods for forming air spacers in integrated circuit devices result in increased parasitic capacitance due to oxidation and damage of barrier layers, as the horizontal portions of sacrificial and protection layers are typically removed after deposition, exposing the bottom portions to chemicals.
Innovation Solution
A method involving the deposition of a sacrificial layer followed by an anisotropic etching process to form a sacrificial ring, then depositing a protection layer and performing another anisotropic etching process to form a protection ring, which prevents oxidation of the barrier layer, followed by the removal of the sacrificial ring to create air spacers with a k value of 1.0, reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If the horizontal portions of sacrificial and protection layers are removed after deposition, then air spacers can be formed, but the bottom portions of barrier layers are exposed to chemicals causing oxidation and damage
Solution Approach 1:
The patent applies preliminary action by performing the etching of sacrificial and protection layers in a specific sequence before complete removal. The protection layer is etched first to expose the barrier layer, then the sacrificial layer is etched to form the air spacer. This preliminary sequencing ensures the barrier layer is exposed only when necessary and protected during subsequent processing, preventing oxidation and damage while still forming the air spacer structure.
Solution Approach 2:
The patent segments the formation process into distinct stages: first etching the protection layer, then etching the sacrificial layer, and finally removing horizontal portions. This segmentation allows precise control over when the barrier layer is exposed to chemicals, limiting oxidation exposure while achieving the desired air spacer geometry.
2Shape
If conventional air spacer formation is used, then dielectric material can be refilled between metal lines, but parasitic capacitance increases due to oxidation of barrier layers
Solution Approach 1:
The patent uses preliminary action by controlling the etching sequence to minimize barrier layer exposure. By etching the protection layer first and then the sacrificial layer in a controlled manner, the barrier layer is exposed only briefly and only where necessary. This prevents oxidation that would increase parasitic capacitance, while still achieving the low-k air spacer structure needed to reduce capacitance between metal lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance between neighboring conductive features by forming air spacers that prevent oxidation and damage to the barrier layers, enhancing the performance and reliability of integrated circuit devices.
Implementation Method 1
performing a first anisotropic etching process to etch the sacrificial spacer layer, performing a second anisotropic etching process to etch the protection layer
Data Source
AI summary
A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.