Air Spacer Formation in Semiconductor Memory Devices
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Solution Overview
Problem
The increasing density of memory cells in DRAM devices leads to smaller distances between components, exacerbating parasite capacitance issues, which complicates the design and manufacturing process, affecting performance and yield.
Innovation Solution
A semiconductor memory device manufacturing method that forms air spacers by removing the first sidewall spacer exposed during the patterning process, effectively reducing parasite capacitance and improving yield and performance by optimizing the etching process to avoid under etching and longer etching times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of memory cells is increased, then the storage capacity is improved, but the distance between components becomes smaller and parasite capacitance increases
Solution Approach 1:
The patent extracts and removes the first sidewall spacer material to form air spacers, effectively removing the harmful parasitic capacitance source while maintaining the high-density memory cell structure. This selective removal allows adjacent bit line structures to be separated by air (vacuum) instead of dielectric material, reducing unwanted electrical coupling.
Solution Approach 2:
The patent introduces air (inert environment) as the spacer material between bit line structures. By replacing traditional dielectric spacer material with air, the parasitic capacitance is minimized since air has much lower dielectric constant, thereby reducing harmful electrical interference while maintaining component density.
2Ease of manufacture
If air spacers are formed after storage node contact pads, then the manufacturing process is simplified, but the formation condition of air spacers cannot be ensured
Solution Approach 1:
The patent performs the action of forming air spacers before creating storage node contact pads. By removing the first sidewall spacer at this earlier stage, the air spacer structure is established in advance, ensuring proper formation conditions are met before subsequent processing steps that might interfere with spacer integrity.
Solution Approach 2:
The patent segments the manufacturing process into distinct stages: first forming air spacers by removing sidewall spacers, then subsequently forming storage node contact pads. This segmentation allows each process step to be optimized independently, ensuring both manufacturing precision for air spacers and overall process simplicity.
3Ease of manufacture
If traditional etching processes are used, then the manufacturing process is straightforward, but under etching occurs and etching time increases
Solution Approach 1:
The patent changes the etching parameters by selecting appropriate etchants and conditions that enable selective removal of the first sidewall spacer material. By optimizing etching parameters such as chemical composition, temperature, and exposure time, the process achieves complete spacer removal without requiring excessive etching time or causing under-etching issues.
Data Source
AI summary
A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.