Air Spacer Wiring Structure for Low Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices become more highly integrated, the distance between wirings decreases, leading to increased parasitic capacitance, which can impede signal transmission and cause galvanic corrosion, necessitating a wiring structure with low parasitic capacitance.
Innovation Solution
A method of manufacturing a semiconductor device with a wiring structure that includes forming conductive patterns and spacers on a substrate, using sacrificial spacers to create air spacers with a low dielectric constant, which reduces parasitic capacitance and prevents galvanic corrosion by isolating the etchant from the conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between wirings is decreased to achieve high integration, then the integration density is improved, but the parasitic capacitance between wirings increases
Solution Approach 1:
An air spacer structure with low dielectric constant is introduced as an intermediary material between adjacent conductive patterns. This air spacer acts as a mediator that reduces the parasitic capacitance coupling between closely spaced wirings while maintaining the high integration density required for advanced semiconductor devices.
Solution Approach 2:
The dielectric constant parameter of the material between conductive patterns is changed from conventional high-k materials to air (k≈1), achieved through the formation of air gaps via sacrificial spacer removal. This parameter change directly reduces parasitic capacitance while allowing continued scaling of wiring pitch for high integration.
2Ease of manufacture
If conventional etching processes are used without proper protection, then the manufacturing process is simplified, but galvanic corrosion occurs between conductive structures
Solution Approach 1:
A mask pattern is introduced as a protective intermediary layer during the etching process. This mask pattern prevents direct contact between the etchant and conductive structures, eliminating galvanic corrosion while maintaining process simplicity. The mask is temporarily applied only during the critical etching step where corrosion would occur.
Solution Approach 2:
The mask pattern is applied in advance before the etching process to preemptively protect conductive structures from galvanic corrosion. By establishing this protective barrier beforehand, the etchant cannot cause corrosion during processing, thus preventing the harmful effect before it can occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively decreases parasitic capacitance between conductive structures, enhancing signal transmission speed and reducing corrosion risks, thereby improving the performance and reliability of semiconductor devices.
Implementation Method 1
air spacers with a low dielectric constant, which reduces parasitic capacitance
Implementation Method 2
prevents galvanic corrosion by isolating the etchant from the conductive structures
Data Source
AI summary
In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.