Air-Void Spacer Structure for MTP Memory Leakage Reduction
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Solution Overview
Problem
Multiple-time programmable (MTP) memory devices using high dielectric "high-k" spacer materials face issues with charge leakage and reduced data retention due to high charge trap centers and parasitic capacitances.
Innovation Solution
The incorporation of air voids within the spacer structure of semiconductor devices, which reduces the effective dielectric constant and minimizes fringing/overlap capacitances, thereby enhancing data retention and preventing charge leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-k spacer materials are used in MTP memory devices, then the dielectric strength is improved, but charge leakage increases and data retention deteriorates due to high charge trap centers and parasitic capacitances
Solution Approach 1:
The spacer structure is segmented into multiple layers with different dielectric materials (first spacer layer with first dielectric material, second spacer layer with second dielectric material). This segmentation allows optimization of each layer's properties to balance dielectric strength and charge trap reduction, resolving the contradiction between dielectric strength and data retention.
Solution Approach 2:
Different regions of the spacer structure are assigned different dielectric materials with specific properties. The first spacer layer uses a material optimized for dielectric strength while the second spacer layer uses a material optimized for lower charge trap centers. This local quality differentiation enables simultaneous achievement of high dielectric strength and low charge leakage.
2Use of energy by moving object
If high-k spacer materials are used, then the capacitance is improved, but fringing/overlap capacitances increase leading to charge leakage
Solution Approach 1:
The spacer is divided into multiple layers with different dielectric materials, allowing the structure to maintain necessary capacitance while reducing fringing/overlap capacitances through optimized material distribution. This segmentation enables control over electric field distribution to minimize charge leakage.
Solution Approach 2:
The spacer structure uses composite materials consisting of different dielectric materials in a layered configuration. This composite approach allows tuning of the overall dielectric properties to achieve desired capacitance while the specific material combination reduces parasitic capacitances and charge leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air voids in the spacer structure effectively reduce charge leakage and improve data retention in MTP memory devices by lowering the dielectric constant and associated capacitances, leading to better performance and longer data retention.
Implementation Method 1
The incorporation of air voids within the spacer structure of semiconductor devices, which reduces the effective dielectric constant and minimizes fringing/overlap capacitances
Data Source
AI summary
A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.