Aircraft Control Assembly With Multi-Core Arbitration Redundancy
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Solution Overview
Problem
Current vehicle control systems, particularly in aircraft, face challenges in efficiently managing redundant hardware and software systems to ensure reliable operation of mission and safety critical functions, especially in gas turbine engines, where concurrent execution of software instructions across multiple cores is not effectively addressed.
Innovation Solution
A multi-core processing architecture is implemented, with each core having localized memory and shared L3 memory accessible through an arbitration module, allowing concurrent execution of discrete sets of software instructions across cores to control aircraft modules, providing redundancy and fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant hardware and software systems are implemented for mission and safety critical functions, then reliability is improved, but device complexity increases
Solution Approach 1:
The system is divided into multiple independent processing cores (first core, second core, third core, fourth core), each capable of independently executing software instructions. This segmentation allows redundant critical functions to be distributed across separate cores, improving reliability while maintaining manageable complexity through modular architecture
Solution Approach 2:
Identical or substantially identical instances of critical software functions are copied and executed on multiple cores simultaneously. The first and second cores each execute the same first discrete set of software instructions, while the third and fourth cores execute the second discrete set, providing redundant computation paths that enhance reliability without requiring entirely separate hardware systems
2Productivity
If concurrent execution of software instructions across multiple cores is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The processor is segmented into four independent cores, each capable of concurrent execution. This allows different discrete sets of software instructions to be processed simultaneously, dramatically improving productivity for mission and safety critical functions that require parallel processing
Solution Approach 2:
Each core is designed with universal functionality to execute any discrete set of software instructions. All cores share common memory resources (first memory, second memory, third memory) and can be dynamically assigned different computational tasks, enabling flexible concurrent execution without requiring dedicated hardware for each function
3Reliability
If localized memory and shared L3 memory are implemented for each core, then reliability is improved, but device complexity increases
Solution Approach 1:
Each core is equipped with its own localized memory (first localized memory for cores 1-2, second localized memory for cores 3-4), providing fast, dedicated storage for frequently accessed data. This local quality ensures that critical computations can proceed without contention, improving reliability while the hierarchical memory structure manages complexity
4Reliability
If arbitration module is implemented to manage memory access, then reliability is improved, but device complexity increases
Solution Approach 1:
An arbitration module is introduced as an intermediary between the cores and the shared memory resources. This mediator manages access conflicts, ensures data consistency, and coordinates memory operations across all four cores, improving reliability through controlled access while centralizing the complexity management in a dedicated component
Data Source
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AI summary
A control assembly (70) for an aircraft system includes a multi-core processor (72) that has a plurality of cores (74) coupled to a communications module (76) and to an arbitration module (78). The communications module (76) is operable to communicate information between the plurality of cores (74) and one or more aircraft modules (AM). The plurality of cores (74) include first and second cores (74-1, 74-2) operable to concurrently execute a first discrete set of software instructions to generate respective instances of an output. The arbitration module (78) is operable to communicate each and every one of the respective instances to control the one or more aircraft modules (AM).