Airgap Etch Stop Layer for IC Capacitance Control
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Solution Overview
Problem
Current airgaps in semiconductor integrated circuits are shallow, leading to inconsistent etch depths and reduced capacitive damping, which increases chip power requirements and interferes with signal transmission due to capacitive coupling between interconnects, and the use of additional barrier layers to control diffusion and electromigration adds resistance and dimensions to interconnects.
Innovation Solution
A robust high-selectivity etch stop layer is introduced between the underlying metal layer and the metal and via layers to allow for uniform and deeper etching of airgaps, preventing over-etching into non-targeted layers and enabling more effective capacitive isolation by increasing the depth of airgaps in low-density areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional barrier layers are used to control diffusion and electromigration, then reliability is improved, but resistance and dimensions of interconnects increase
Solution Approach 1:
The patent extracts the barrier layer from the interconnect structure by replacing it with airgaps. The airgaps are formed by removing dielectric material between interconnect lines, creating voids that naturally prevent diffusion and electromigration without adding resistive barrier layers. This extraction eliminates the need for additional barrier materials while maintaining interconnect dimensions.
Solution Approach 2:
The patent uses airgaps (inert atmosphere) between interconnects to prevent diffusion and electromigration. The air or vacuum within the gaps acts as a barrier to atomic diffusion and electron migration, providing the same protective function as traditional barrier layers but without increasing interconnect resistance or dimensions.
2Loss of energy
If airgap depth is increased to improve capacitive isolation, then capacitance is reduced, but etch consistency becomes difficult to maintain
Solution Approach 1:
The patent applies preliminary action by forming an etch stop layer before performing the airgap etching process. This etch stop layer is deposited at a controlled depth and prevents the etch from going deeper than intended, ensuring consistent airgap depths across the wafer. The etch stop layer acts as a pre-established barrier that guarantees etch depth uniformity.
Solution Approach 2:
The etch stop layer provides feedback control for the etching process. When the etch reaches the etch stop layer, the etch rate changes or stops, providing real-time feedback that the target depth has been achieved. This feedback mechanism ensures consistent airgap depths without requiring complex real-time monitoring systems.
3Loss of energy
If airgap depth is increased to improve capacitive isolation, then energy loss is reduced, but underlying metal layers may be damaged
Solution Approach 1:
The etch stop layer is deposited in advance before the airgap etching process, establishing a protective barrier that prevents the etch from damaging underlying metal layers. This preliminary action ensures that the etch will stop at the correct depth, protecting the metal layers while still achieving sufficient airgap depth for capacitive isolation.
Solution Approach 2:
The etch stop layer acts as a cushioning layer that absorbs the etching process, preventing it from penetrating too deep and damaging the underlying metal layers. This beforehand cushioning provides a safety margin that protects the metal layers while allowing deep airgaps to be formed for effective capacitive isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves capacitance benefits of 10-40% by ensuring consistent airgap depths across the IC, reducing capacitive coupling and enhancing signal transmission while maintaining the integrity of underlying metal layers.
Implementation Method 1
capacitive coupling between interconnects
Implementation Method 2
The insulating material may include oxides, low-K materials, and the like
Data Source
AI summary
An embodiment includes first, second, and third metal layers; first, second, and third metal lines included in the second metal layer; a layer including airgaps, the first metal layer being between the layer including airgaps and the second metal layer; a first void between the first and second metal lines and a second void between the second and third metal lines; a conformal layer between the first and second metal lines; an additional layer between the first and second metal layers; wherein the first void includes air and the second void includes air; wherein a first axis intersects the first, second, and third metal lines and the first and second voids; wherein a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer; wherein a third axis, orthogonal to the first axis, intersects the second metal line and the additional layer.