Airgap Spacer FET Structure With T-Shaped Gate for Low Capacitance
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Solution Overview
Problem
Conventional field-effect transistors exhibit high off-capacitance and low breakdown voltage, which negatively impact device performance.
Innovation Solution
A structure for a field-effect transistor is developed, featuring a T-shaped gate electrode with varying widths and airgaps between the gate electrode and raised source/drain regions, which reduces overlap capacitance and increases breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional field-effect transistor structure is used, then device simplicity is maintained, but off-capacitance is high and breakdown voltage is low
Solution Approach 1:
The gate electrode is segmented into two distinct sections: a first section with greater width and a second section with lesser width. This segmentation allows each section to serve different functional purposes, with the wider section providing enhanced breakdown voltage and the narrower section reducing overlap capacitance, thereby resolving the technical contradiction between reliability and device complexity.
Solution Approach 2:
Different sections of the gate electrode are given different widths to create local quality variations. The first section has a greater width to increase breakdown voltage in regions requiring higher reliability, while the second section has a lesser width to reduce overlap capacitance where speed and efficiency are prioritized. This local differentiation resolves the contradiction by optimizing different regions for different performance characteristics.
2Reliability
If conventional gate electrode structure is used, then manufacturing simplicity is maintained, but overlap capacitance is high
Solution Approach 1:
The gate electrode is divided into two sections with different widths, where the first section has greater width and the second section has lesser width. This segmentation reduces the overlap area between the gate electrode and source/drain regions, thereby reducing off-capacitance. The segmentation is achieved through standard photolithography and etching processes, maintaining ease of manufacture while improving electrical performance.
Solution Approach 2:
The width parameter of the gate electrode is changed across different sections, with the first section having a greater width and the second section having a lesser width. This parameter variation optimizes the balance between breakdown voltage and overlap capacitance. The width changes are implemented through controlled fabrication processes, ensuring that the parameter modification does not significantly complicate manufacturing.
3Reliability
If uniform width gate electrode is used, then structural simplicity is maintained, but both breakdown voltage and overlap capacitance performance are suboptimal
Solution Approach 1:
The gate electrode is segmented into two sections with different widths to simultaneously optimize breakdown voltage and overlap capacitance. The first section with greater width enhances breakdown voltage, while the second section with lesser width reduces overlap capacitance. This segmentation creates a non-uniform geometry that improves overall device performance compared to a uniform width gate electrode.
Solution Approach 2:
The gate electrode employs asymmetric geometry with the first section having greater width and the second section having lesser width. This asymmetry is strategically designed to optimize electrical performance: the wider section provides enhanced breakdown voltage for improved reliability, while the narrower section reduces overlap capacitance for better switching performance. The asymmetric shape resolves the contradiction between structural simplicity and device performance.
Data Source
AI summary
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.