Air-Gap Interconnects With Pillar Support For Capacitance Reduction
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Solution Overview
Problem
Current via manufacturing technologies face challenges such as increased capacitive coupling between interconnect lines and vias due to scaling, leading to short-circuit risks and ineffective reduction in layer-to-layer capacitance, particularly with dry etching processes that leave dielectric material behind and require additional masking.
Innovation Solution
The implementation of a method that forms floating interconnect lines with air-gaps between and below them, supported by pillars and vias, using a sacrificial material layer and permeable etchstop layers to prevent unlanded vias from breaking through and reduce capacitive coupling, eliminating the need for additional masking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If air-gap etching is used to reduce capacitance, then capacitive coupling is reduced, but the risk of short-circuits increases due to unlanded vias
Solution Approach 1:
A sacrificial material layer is introduced as an intermediary between the air-gap etching process and the via formation. This sacrificial layer prevents direct contact between unlanded vias and the underlying layer, eliminating the short-circuit risk while allowing the air-gap etching to proceed for capacitance reduction. The sacrificial material is later removed to complete the via formation.
Solution Approach 2:
The air-gap etching process is performed preliminarily before via formation. By creating the air-gaps first and then forming vias through the sacrificial material, the process ensures that the capacitance reduction is achieved while the sacrificial material protects against short-circuits during the subsequent via formation step.
2Manufacturing precision
If dry etching is used for air-gap formation, then anisotropic etching is achieved, but dielectric material remains behind and layer-to-layer capacitance is not reduced
Solution Approach 1:
The etching process is segmented into two distinct steps: first, anisotropic dry etching creates lateral air-gaps between interconnect lines with high precision; second, isotropic etching removes the sacrificial material to create vertical air-gaps below the interconnect lines. This segmentation allows each etching step to optimize for its specific purpose while achieving complete capacitance reduction.
Solution Approach 2:
The etching parameters are changed between the two etching steps. The first step uses anisotropic etching conditions (directional plasma, specific gas chemistry) to achieve precise lateral etching. The second step uses isotropic etching conditions (different gas chemistry, non-directional plasma) to remove the sacrificial material vertically, creating the second air-gap dimension.
3Reliability
If additional masks are used to prevent shorting, then short-circuit risk is reduced, but manufacturing complexity increases
Solution Approach 1:
The sacrificial material layer serves a dual function: it acts as a protective barrier during via formation to prevent short-circuits, and simultaneously serves as the etch mask for creating the vertical air-gaps. This self-service approach eliminates the need for separate masking steps, reducing manufacturing complexity while maintaining reliability.
Solution Approach 2:
The sacrificial material layer performs multiple functions within the process sequence: it protects against short-circuits during via formation, serves as the etch mask for vertical air-gap creation, and is later removed to complete the via holes. This multi-functionality consolidates multiple process steps into a single material layer, simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces line-to-line and layer-to-layer capacitive coupling, enhancing the structural integrity and reducing the risk of short-circuits by creating self-aligned etchstop layers and air-gaps, thereby improving the manufacturing process for semiconductor devices.
Implementation Method 1
removing the sacrificial material layer through the permeable etchstop layer
Implementation Method 2
Air-gaps may be used to replace portions of the low k-dielectric materials in order to further decrease the capacitance
Data Source
AI summary
Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.