Airgap Interconnects with Dielectric-Capped Cavities

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Solution Overview

Problem

The existing methods for forming airgaps in interconnect structures during semiconductor device fabrication often damage the metal lines, leading to increased resistance due to corner erosion during the etching process, which defeats the purpose of reducing capacitance.

Innovation Solution

A method involving the selective deposition of a dielectric layer on interconnects and the subsequent removal of specific sections of this layer to create cavities with encapsulating airgaps, where a conformal dielectric layer pinches off at the entrance to prevent metal erosion and maintain low capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If an etching process is used to remove the interlayer dielectric layer between the lines and define cavities for airgaps, then capacitance is reduced, but the metal lines are damaged leading to increased resistance

Engineering Contradiction:
ImprovecapacitanceVSAvoidmetal line integrity
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

A conformal dielectric layer is deposited as an intermediary protective coating on the metal lines before the etching process. This layer acts as a mediator that protects the metal from direct exposure to the etching chemistry, preventing erosion and corner damage while still allowing the etch to proceed and form airgap cavities between the lines.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The conformal dielectric layer is deposited in advance before the cavity-forming etch process. This preliminary action prepares the metal lines with a protective coating that will prevent damage during the subsequent etching step, ensuring that the lines maintain their integrity while the airgaps are formed.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If an over-etch is required to remove the interlayer dielectric layer completely, then airgaps are properly formed, but corner erosion of metal lines increases

Engineering Contradiction:
Improveairgap formationVSAvoidmetal line geometry
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The conformal dielectric layer serves as a protective intermediary that allows the etching process to proceed with sufficient over-etch to completely remove the interlayer dielectric and form proper airgaps, while the layer itself prevents the etch from attacking and eroding the metal line corners.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The conformal dielectric layer provides beforehand cushioning or protection to the metal lines against the harmful effects of over-etching. This protective layer absorbs the excessive etching action, allowing complete removal of the interlayer dielectric for proper airgap formation while cushioning the metal lines from damage.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces capacitance by preventing metal line erosion and maintaining low resistance, thereby enhancing the performance of interconnect structures.

Implementation Method 1

A conformal dielectric layer is deposited that coats the surfaces surrounding the cavities and pinches off at the cavity entrances to surround and encapsulate the airgaps

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

An etching process is used to remove the interlayer dielectric layer between the lines and define cavities in regions where airgaps are desired

Methodology Applied
Scientific EffectErosion: Erosion

Data Source

PatentUS20200227308A1Interconnect structures with airgaps and dielectric-capped interconnects
Publication Date: 2020.07.16 GLOBALFOUNDRIES US INC
  • US20200227308A1 patent drawing
  • US20200227308A1 patent drawing
  • US20200227308A1 patent drawing

AI summary

Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.