Airgap Interconnects for Parasitic Coupling Reduction
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing parasitic coupling between metal wires due to high dielectric constants, leading to noise and reliability issues, especially with the aggressive scaling of interconnect pitch sizes, and the use of low-k dielectrics which have weak mechanical properties and reliability concerns.
Innovation Solution
The formation of airgaps between metal wires using a method that involves forming adjacent wires in a dielectric layer, creating a masking layer with the same dimensions as the wires, and etching to form trenches, allowing an interlevel dielectric layer to pinch off and create airgaps, which reduces parasitic coupling and enhances electro-migration and dielectric breakdown strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low-k dielectric films are used to reduce parasitic coupling, then the dielectric constant is reduced, but the mechanical strength and reliability deteriorate
Solution Approach 1:
The patent combines low-k dielectric material with airgap (vacuum) to create a composite interlevel dielectric structure. The airgap portion provides extremely low dielectric constant (k≈1) while the remaining dielectric material provides mechanical support, achieving both low parasitic coupling and adequate structural integrity
Solution Approach 2:
Instead of using low-k material throughout the entire interlevel dielectric, the patent creates localized airgaps only in critical regions where parasitic coupling needs to be reduced (between adjacent wires), while other regions maintain sufficient dielectric material for mechanical strength
2Productivity
If interconnect pitch size is reduced for technology scaling, then device density increases, but parasitic coupling increases due to closer wire spacing
Solution Approach 1:
The patent applies airgap formation selectively between adjacent wires in high-density interconnect regions, providing localized parasitic coupling reduction exactly where needed due to aggressive scaling, while maintaining overall device density benefits
3Object-affected harmful factors
If wires are separated to reduce parasitic coupling, then coupling decreases, but device density and circuit speed deteriorate
Solution Approach 1:
The patent creates a composite interlevel dielectric with airgap portions that provide extreme electrical isolation (k≈1) between wires, enabling sufficient wire separation for reduced coupling while maintaining compact layout for high circuit speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic coupling, improves electro-migration, and enhances dielectric breakdown reliability, enabling faster digital circuits with higher operating frequencies and currents without compromising reliability, by creating airgaps that can be formed in smaller technology nodes and providing metal shielding to reduce electric fields.
Implementation Method 1
forming an interlevel dielectric layer upon the dielectric layer, wherein the interlevel dielectric layer is pinched off from filling the trenches so that an airgap is formed between the adjacent wires
Implementation Method 2
metal liners formed near sidewalls of the adjacent wires... providing metal shielding to reduce electric fields
Data Source
AI summary
Semiconductor structures with airgaps and/or metal linings and methods of manufacture are provided. The method of forming an airgap in a wiring level includes forming adjacent wires in a dielectric layer. The method further includes forming a masking layer coincident with the adjacent wire and forming a first layer on the masking layer to reduce a size of an opening formed in the masking layer between the adjacent wires. The method further includes removing exposed portions of the first layer and the dielectric layer to form trenches between the adjacent wires. The method further includes forming an interlevel dielectric layer upon the dielectric layer, where the interlevel dielectric layer is pinched off from filling the trenches so that an airgap is formed between the adjacent wires. A metal liner can also be formed in the trenches, prior to the formation of the airgap.