Airgap Isolation for Bulk Substrate RF Switches

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Solution Overview

Problem

Integrating RF switches into bulk substrates is challenging due to the need to drop large voltages across junctions and the presence of large depletion layers, which add substantial area to the layout, unlike silicon on insulator (SOI) substrates.

Innovation Solution

A method involving the formation of an amorphous layer and an airgap in a bulk substrate, creating a completely isolated transistor with an underlying airgap, eliminating the need for junctions between the transistor and the substrate by using shallow trench isolation and deep trench structures to form an airgap underneath the transistor channel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If RF switches are integrated into bulk substrates using conventional methods, then the device can be manufactured in standard bulk process, but large depletion layers add substantial area to the layout

Engineering Contradiction:
Improveintegration into bulk processVSAvoidlayout area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The invention extracts the substrate material directly beneath the transistor channel by forming deep trenches and removing the silicon, replacing it with an airgap. This removes the source of large depletion layers while maintaining bulk process compatibility, thereby reducing layout area without sacrificing manufacturability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention changes the physical parameter of the substrate region under the transistor from solid silicon to airgap (vacuum). This parameter change eliminates the need for large depletion layers in high resistivity substrates, reducing the required layout area while maintaining electrical isolation

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If RF switches are integrated into bulk substrates, then the device can be manufactured in standard bulk process, but large voltages must be dropped across junctions

Engineering Contradiction:
Improveintegration into bulk processVSAvoidvoltage drop across junctions
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

By removing the substrate silicon beneath the transistor and replacing it with an airgap, the invention eliminates the pn junction between the well and substrate. This extraction removes the harmful voltage drop across junctions while maintaining compatibility with standard bulk manufacturing processes

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The airgap acts as an intermediary between the transistor and the bulk substrate, providing electrical isolation without requiring a pn junction. This mediator eliminates the voltage drop issue while allowing the device to be manufactured in standard bulk processes

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-generated harmful factors

If airgap is formed under the transistor channel, then voltage drop across junctions is prevented, but the device complexity increases

Engineering Contradiction:
Improvevoltage drop across junctionsVSAvoidstructure complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The invention segments the substrate by forming deep trenches that isolate the region beneath the transistor channel. This segmentation creates discrete airgap regions that can be precisely controlled, achieving voltage isolation while managing structural complexity through systematic division of the substrate

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach fully isolates the FET, preventing voltage drop across well-to-substrate junctions and reducing layout area, allowing for efficient integration of RF switches into standard bulk silicon processing without disturbing adjacent elements.

Implementation Method 1

an amorphous layer under an active region of a substrate

Methodology Applied
Scientific EffectEtch barrier:

Implementation Method 2

fully isolates the FET, preventing voltage drop across well-to-substrate junctions

Methodology Applied
Scientific EffectElectrical isolation:

Data Source

PatentUS10692753B2Semiconductor structure with airgap
Publication Date: 2020.06.23 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10692753B2 patent drawing
  • US10692753B2 patent drawing
  • US10692753B2 patent drawing

AI summary

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.