Airgap Spacer FET Structure for Lower Parasitic RC
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Solution Overview
Problem
As integrated circuits shrink in size, parasitic capacitance and resistance increase, leading to undesirable effects like RC delay and power dissipation, and traditional methods for forming airgap spacers and wrap-around contacts either compromise the high-k/metal gate stack or result in high contact via resistance.
Innovation Solution
A semiconductor structure is formed with self-aligned sacrificial cap layers and thinner sacrificial spacers that allow for simultaneous formation of airgap spacers and wrap-around contacts, preserving the high-k/metal gate stack and reducing contact via resistance by removing low-k spacer material from gate sidewalls and forming airgaps with a wider bottom portion between the gate and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions and component spacing are shrunk to increase device density, then device density is improved, but parasitic capacitance and parasitic resistance increase causing RC delay and power dissipation
Solution Approach 1:
The patent extracts the harmful dielectric material between the gate structure and source/drain regions by forming airgap spacer structures. The airgap spacer removes the solid dielectric material that contributes to parasitic capacitance, replacing it with air or vacuum which has negligible dielectric properties, thereby reducing parasitic capacitance and RC delay while maintaining scaled device dimensions
Solution Approach 2:
The airgap spacer structure creates a porous or void space between the gate and source/drain regions. This porous structure filled with air or vacuum acts as an insulator with minimal dielectric constant, reducing parasitic capacitance while allowing the device to maintain small dimensions for high density
2Ease of manufacture
If traditional methods are used to form airgap spacers and wrap-around contacts, then airgap structure is achieved, but the high-k/metal gate stack is compromised or contact via resistance is high
Solution Approach 1:
The patent performs preliminary actions by forming the airgap spacer structure before forming the contact structures. The airgap spacer is created using a sacrificial layer that is removed to form the airgap, and this is done prior to forming the contacts that wrap around the source/drain regions. This sequence allows the high-k/metal gate stack to be preserved while enabling subsequent contact formation with reduced resistance
Solution Approach 2:
The patent segments the spacer formation process into multiple stages: first forming a bottom spacer, then forming an airgap spacer structure, and finally forming a top spacer. This segmentation allows precise control over the airgap formation while preserving the gate stack integrity and enabling separate optimization of contact structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and resistance while maintaining the integrity of the high-k/metal gate stack, enhancing device performance and reliability by increasing airgap size and contact area.
Implementation Method 1
parasitic capacitance and parasitic resistance increase, causing undesirable effects such as RC delay
Data Source
AI summary
A field effect transistor includes a gate structure formed adjacent to a source/drain region, and a spacer structure formed between the gate structure and the source/drain region. The spacer structure includes a top spacer and a bottom spacer, the top spacer includes an airgap having a bottom portion that is wider than a top portion. The wider bottom portion of the airgap is located between the gate structure and the source/drain region.