Airgap Spacer Structure for Lower Gate-to-Contact Capacitance
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Solution Overview
Problem
As integrated circuits shrink, parasitic capacitance between transistor gate structures and adjacent metallic contacts increases, degrading transistor performance and making it challenging to fabricate high-density semiconductor devices due to the high dielectric constant of traditional spacer materials.
Innovation Solution
Replacing traditional spacer structures with airgaps or low-k dielectric materials between gate structures and source/drain contacts to reduce parasitic capacitance, using techniques such as isotropic etching to create voids with a dielectric constant of around 1.0 or filling them with low-k dielectric materials, thereby reducing the dielectric constant between 1.0 and 3.4.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional spacer structures with high dielectric constant materials are used, then structural support and separation are provided, but parasitic capacitance increases degrading transistor performance
Solution Approach 1:
The patent removes the traditional spacer structure entirely and replaces it with an airgap formed by selective etching. This extraction eliminates the high dielectric constant material that causes parasitic capacitance, directly resolving the contradiction between needing structural separation and avoiding harmful capacitive effects.
Solution Approach 2:
The patent changes the dielectric constant parameter from high (traditional spacer materials) to approximately 1.0 (airgap). This parameter change dramatically reduces parasitic capacitance while maintaining the necessary physical separation between gate structures and source/drain contacts.
2Productivity
If device spacing is reduced to increase density, then more transistors can be packed, but parasitic effects from adjacent conductive structures increase
Solution Approach 1:
The airgap acts as an intermediary region between adjacent conductive structures (gate and source/drain contacts). This intermediate space with minimal dielectric constant reduces the parasitic coupling effects that would otherwise increase with reduced spacing, enabling higher device density without proportional increase in parasitic effects.
3Reliability
If airgap is introduced to reduce parasitic capacitance, then transistor performance improves, but fabrication complexity increases
Solution Approach 1:
The patent incorporates spacer formation as a preliminary action during the standard fabrication sequence, before final contact formation. The sacrificial spacers are deposited and patterned early in the process, then selectively removed to create airgaps. This preliminary positioning of spacer structures enables subsequent airgap formation without requiring entirely new fabrication equipment or processes.
Solution Approach 2:
The patent replaces the mechanical/spatial problem of maintaining precise airgap dimensions with a chemical solution using selective etching. Instead of relying on mechanical precision to create and maintain airgaps, the process uses chemical etchants that selectively remove sacrificial spacer materials, allowing airgap formation through chemical selectivity rather than mechanical control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhancing transistor switching speeds and overall performance by creating a low dielectric constant region between gate structures and source/drain contacts, facilitating the fabrication of high-density semiconductor devices.
Implementation Method 1
parasitic capacitance between transistor gate structures and adjacent metallic contacts increases... replacing traditional spacer structures with airgaps or low-k dielectric materials... to reduce parasitic capacitance... creating a low dielectric constant region
Data Source
AI summary
Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction. Airgaps are provided in the regions between the gate structures and the adjacent source/drain contacts. The airgaps have a low dielectric constant (e.g., around 1.0) to reduce the parasitic capacitance between the conductive structures.